IBM System/370 Guide

Doubleword - 8 bytes - 72 bits
Doubleword - 8 bytes - 72 bits
--
...............
---
...-
~
---
8 bits
8 bits
64 Data Bits
of
64 Data Bits
of
ECC code ECC code
\ Storage Address
is a Multiple of B
Figure 50.10.1. Data representation used in Model 165 processor storage
Doubleword - 8 bytes - 72 bits
Doubleword - 8 bytes - 72 bits
---------- .. ------~------ .... ---------
8 Data Bits
~
Byte'
*Parity Bit
Figure 50.10.2.
8 Data Bits
8 Data Bits
Byte 8
8 Data Bits
,.
-------------
Byte 8
Data representation used in Models 65 and 75 and
in the Model 165 in other than processor storage
Data enters and leaves processor storage through the storage adapter
unit, which performs ECC validity checking on each doubleword. When
a doubleword (72 bits> is fetched from processor storage, the storage
adapter unit checks the 8-bit ECC code to validate the 64 data bits.
If the data is correct, the adapter unit generates the appropriate
parity bit for each of the 8 data bytes and reformats the doub1eword
to look as shown in Figure 50.10.2. If a single-bit error is detected,
the identified data bit in error is corrected automatically by the
corrector unit in the storage adapter. The corrected doub1eword is
sent back to processor storage and on to the storage control unit.
When a doub1eword is to be placed in processor storage, the storage
adapter unit strips the a parity bits, constructs the necessary a-bit
ECC code, and appends the code to the 64 data bits. The 72 bits are
then stored as shown in Figure 50.10.1.
When a single-bit storage ,error is detected and corrected during
the execution of an instruction or I/O operation, a soft machine check
latch is turned on and execution continues. At the completion of the
operation a machine check interrupt occurs to allow error recording
to be done unless ECC correction interrupts have been disabled.
When a doub1e- or a multiple-bit processor storage error involving
the CPU is detected, a machine check interrupt occurs. The MCH routine
logs the error and attempts recovery procedures. When a double- or
multiple-bit processor storage error occurs during an I/O operation,
both a machine check and an I/O interrupt occur so that both error
recording and I/O retry procedures can be executed.
72

IBM System/370 Specifications

General

Brand	IBM
Model	System/370
Category	Server
Language	English