Integra DTR-6.4 - Page 63

DTR-6.4
IC BLOCK DIAGRAMS AND DESCIRPIONS
CS5333(24-Bit, 96 kHz Stereo A/D Converter)
VL
MCLK
SCLK
SDATA
VA
GND
LRCK
DIV
RST
VQ
AINL
AINR
REF-GND
FILT+
TST
DIF
Reset
Quiescent Voltage
Left Channel Analog Input
Right Channel Analog Input
Reference Ground
Positive Voltage Reference
Test Input
Digital Interface Format
Interface Power
Master Clock
Serial Clock
Serial Data Output
Analog Power
Ground
Left Right Clock
MCLK Divide
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDATA
LRCK
SCLK
S/H
LP Filter
DAC
Comparator
Digital Decimation
Filter
HPF
S/H
LP Filter
DAC
Comparator
Digital Decimation
Filter
HPF
VA VL RST
AINL
AINR
TST GND VQ MCLK FILT+ REF-GND DIV
DIF
Serial Port
uPD4721GS (RS-232C Driver/ Receiver)
1
2
3
4
5
6
7
8
9
10
5.5k ohm
5.5k ohm
300 ohm
300 ohm
V DD
C 1
V CC
C 1
C S
C S
D IN1
D IN2
R OUT1
R OUT2
C 4
GND
C 4
V SS
STBY
V CHA
D OUT1
D OUT2
R IN1
R IN2
20
19
18
17
16
15
14
13
12
11
Block diagram
Truth table
STBY
L
H
H
DIN
X
L
H
DOUT
Z
H
L
Standby mode (DC/DC converter is stopped)
Space level output
Mark level output
Remarks
Driver
Receiver
STBY
L
H
H
R
IN
X
L
H
R
OUT
H
H
L
Standby mode (DC/DC converter is stopped)
Space level input
Space lev
el input
Remarks
3 V/5 V switching
V
CHA
L
H
Oper
ating mode
5 V mode (double step-up)
3 V mode (3 times step-up)