Intel 80960KB

80960KB
34
Figure 28. Burst Read and Write Transaction Without Wait States
T
a
T
d
T
d
T
r
T
a
T
d
T
d
T
d
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY