Intel 80960KB

80960KB
35
Figure 29. Burst Write Transaction with 2, 1, 1, 1 Wait States
T
a
T
w
T
w
T
d
T
w
T
d
T
w
T
d
T
w
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY