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Intel

Server Board S5500BC TPS Glossary

Revision 1.0 Intel order number: E42249-003 107

Term Definition

SNMP Simple Network Management Protocol

TBD To Be Determined

TIM Thermal Interface Material

UART Universal Asynchronous Receiver/Transmitter

UDP User Datagram Protocol

UHCI Universal Host Controller Interface

UTC Coordinated Universal Time

VID Voltage Identification

VRD Voltage Regulator Down

Word 16-bit quantity

ZIF Zero Insertion Force

Main Page

Table of Contents3
Introduction12
Server Board Use Disclaimer12
Product Overview13
Feature Set13
Server Board Layout15
Server Board Connector and Component Layout15
Figure 1. Intel Server Board S5500BC Picture15
Figure 2. Intel16
Table 1. Board Layout Reference16
Server Board Mechanical Drawing17
Figure 3. Key Connector and LED Indicator Identification17
Figure 4. Mounting Hole Location18
Figure 5. Major Connector Pin-1 Locations19
Figure 6. S5500BC Board Primary Side Keepouts20
Figure 7. S5500BC Board PRIMARY SIDE CARD-SIDE KEEPOUT ZONE21
Figure 8. Secondary Side Keepout -- Mounting Hole Keepout22
Figure 9. Secondary Side Keepout - CPU Socket and Rubber Pad Keepout23
Intel ® Light-Guided Diagnostic LED Locations24
Light-Guided Diagnostic LED Reference24
External I/O Connector Locations25
Figure 10. Intel25
Figure 11. External I/O Layout25
Table 3. External I/O Layout Reference25
Functional Architecture26
Processor Sub-System26
Figure 12. Functional Block Diagram26
Intel ® Quickpath Interconnect (QPI)27
Table 4. Intel ® Xeon ® Processor 5500 Series Feature Set Overview27
Processor Population Rules28
Figure 13. Intel ® IOH 5500 Chipset with Intel ® Quickpath Interconnect Block Diagram28
Table 5. Mixed Processor Configurations29
Multiple Processor Initialization30
Turbo Mode31
Simultaneous Multi-Threading31
Enhanced Intel Speedstep Technology31
Multi-Core Processor Support32
Independent Loading Mechanism (ILM) Back Plate Design Support32
Memory Sub-System33
Integrated Memory Controller33
Figure 14. ILM Backplate and URS33
DIMM Population Requirements34
Figure 15. DIMM Organization34
Figure 16. Channel Slots Configuration35
Memory Upgrade Guidelines36
Table 6. DIMM Population Configurations36
Support for Mixed-Speed Memory Modules37
CPU Cores, QPI Links and DDR3 Channels Frequency Configuration37
Memory RAS Features37
Independent Channel Mode38
Channel Mirroring Mode38
Lockstep Channel Mode38
Demand and Patrol Scrub39
Intel I/O Hub (IOH) 5500 Chipset39
Table 7. Intel IOH 5500 Chipset Features39
PCI Express* Gen 240
Enterprise South Bridge Interface (ESI) Features40
Controller Link (M-Link)40
Management Engine (ME)40
VT-D) (Rev. 2)41
Intel ® 82801Jx I/O Controller Hub (ICH10R)42
PCI and PCI Express* Interfaces42
Serial ATA II Interface43
Software RAID Support43
Low Pin Count Interface (LPC)44
Serial Bus (USB) Controller44
Serial Peripheral Interface (SPI)44
General Purpose Input/Output (GPIO)44
Enhanced Power Management44
System Management Interface45
Real Time Clock (RTC)45
Manageability45
Unsupported Intel ICH10R Interfaces45
Network Interface Controller (NIC)46
Table 8. NIC Status LED46
Intel ® 82574L Gbe PCI-E Network Controller47
Intel ® 82567 Gigabit Network Connection Physical Layer Transceiver (PHY)47
MAC Address Definition47
Integrated Baseboard Management Controller48
Integrated BMC Embedded LAN Channel50
Figure 17. Integrated BMC Block Diagram50
Video Support51
Video Modes51
Serial Ports51
Floppy Disk Controller51
Table 9. Video Modes51
3.10 Keyboard and Mouse Support52
3.11 Wake-Up Control52
3.12 System Health Support52
Platform Management53
Figure 18. SMBUS Block Diagram54
Feature Support55
IPMI 2.0 Features55
Non-IPMI Features55
Advanced Management Feature Support56
Enabling Advanced Management Features56
Keyboard, Video, Mouse (KVM) Redirection57
Media Redirection57
Availability58
Web Services for Management (WS-MAN)58
Local Directory Authentication Protocol (LDAP)58
Embedded Web Server58
Console Redirection59
Serial Configuration Settings59
SOL, EMP and Console Redirection Use Case Model59
Node Manager60
Overview60
Command Bridging60
External Communications Link61
Alerting61
System Information Passed to ME and POST Complete Notification61
ACPI Mode Notification62
Persistence Across Boots62
Power Management Bus (PMBUS)62
Connector / Header Locations and Pin-Outs63
Board Connectors63
Power Connectors63
Table 10. Board Connector Matrix63
Table 11. EPS12V 2X12 Connector (J9B3)64
Table 12. EPS12V 2X4 Connector (J7K1)64
Riser Card Slot65
Table 13. EPS12V 1X5 Connector (J9E1)65
Table 14. Low-Profile PCI Riser Card Pin-Out (J3C1)65
RMM3 Connector66
Table 15. RMM3 Connector Pin-Out (J3C1)66
SSI Front Panel Connector67
I/O Connector Pin-Out Definition67
VGA Connector67
Table 16. Front Panel SSI Standard 24-Pin Connector Pin-Out (J9E2)67
SATA II Connectors68
Table 17. VGA Connector Pin-Out (J7A1)68
Table 18. SATA Connector Pin-Out (J1B4, J1B3, J1A2, J1B1, J1B2, and J2B1)68
Serial Port Connectors69
USB and Gige Connector69
Table 19. 9-Pin External Serial a Port Header Pin-Out (J8A1)69
Table 20. Internal Serial B Port Header Pin-Out (J9A1)69
Table 21. External USB and Gbe Connector Pin-Out (J5A1, J6A1)70
Table 22. Internal USB Header Pin-Out (J1A3, J2A2)70
Fan Headers71
SGPIO Header72
Chassis Intrusion Header72
5.10 SMB Hot-Swap Backplane (HSBP) Header72
Table 24. SGPIO Connector Pin-Out (J1C1)72
Table 25. Chassis Intrusion Connector Pin-Out (J8B3)72
Table 26. SMB HSBP Connector Pin-Out (J9B1)72
5.11 SATA RAID Key Header73
5.12 IPMB Header73
Table 27. SATA Connector Pin-Out (J7B1)73
Table 28. IPMB Connector Pin-Out (J8B1)73
Jumper Block Settings74
Figure 19. Jumper Blocks74
Table 29. Jumper Block Matrix74
Intel Light-Guided Diagnostics76
5-Volt Standby LED76
System ID and Status LED76
DIMM Fault Leds77
Table 30. System Status LED Indicator States77
Fan Fault Leds78
Post Code Diagnostic Leds78
Table 31. DIMM Leds Indicator States78
Table 32. Fan LED Indicator States78
Power and Environmental Specifications79
Intel ® Server Board S5500BC Design Specifications79
Baseboard Power Requirements79
Table 33. Server Board Design Specifications79
Figure 20. Power Distribution Block Diagram80
Power Requirements81
8.2.2 Turn on no Load Operation81
Grounding81
Table 34. no Load Operating Range81
Standby Outputs82
Remote Sense82
Voltage Regulation82
Dynamic Loading83
Capacitive Loading83
Closed-Loop Stability83
Table 35. Voltage Regulation Limits83
Table 36. Transient Load Requirements83
Table 37. Capacitive Loading Conditions83
Common Mode Noise84
Ripple / Noise84
Soft Starting84
Timing Requirements84
Table 38. Ripple and Noise84
Figure 21. Output Voltage Timing85
Table 39. Output Voltage Timing85
Table 40. Turn On/Off Timing85
Residual Voltage Immunity in Standby Mode86
Figure 22. Turn On/Off Timing (Power Supply Signals)86
Regulatory and Certification Information87
Product Regulatory Compliance87
Product Safety Compliance87
Product EMC Compliance - Class a Compliance88
Certifications / Registrations / Declarations88
Product Ecology Requirements88
Product Regulatory Compliance Markings90
9.3 Electromagnetic Compatibility Notices92
FCC Verification Statement (USA)92
ICES-003 (Canada)93
Europe (CE Declaration of Conformity)93
VCCI (Japan)93
BSMI (Taiwan)94
RRL (Korea)94
CNCA (CCC-China)94
Appendix A: Integration and Usage Tips95
Appendix B: Sensor Tables96
Table 41. Integrated BMC Core Sensors97
Appendix C: POST Error Messages and Handling105
Table 42. POST Error Messages and Handling105
Table 43. POST Error Beep Codes108
Appendix D: POST Code Diagnostic LED Decoder110
Figure 23. Diagnostic LED Placement Diagram110
Table 44. POST Progress Code LED Example110
Table 45. Diagnostic LED POST Code Decoder111
Appendix E: Intel Server System SR1630BC114
Figure 24. 1U Intel ® Server System SR1630BC Overview114
Appendix F: Supported Intel Server Chassis SC5650115
Figure 25. 5U Intel Entry Server Chassis SC5650 Overview115
Glossary116
Reference Documents119

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