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GD82559ER
Intel GD82559ER User Manual
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Datashee
t
85
Networking Silicon — GD825
59ER
12.
P
acka
g
e and Pinout Information
12.1
P
acka
ge Inf
ormation
The GD82559ER
is a 196-pin Ball Grid Ar
ray (BGA) package.
Package dimension
s are sho
wn in
Figur
e 24
. More information on In
tel device
packaging is a
v
ailable in the Intel Pac
kaging
Handbook, which is av
ailable from the Intel Literature Center or your local Intel sales off
ice.
Figure 24. Dimens
ion Diagram f
or the GD825
59ER 196-Pi
n BGA
90
92
Table of Contents
Default Chapter
1
Product Features
1
Revision History
2
Table of Contents
3
1 Introduction
7
GD82559ER Overview
7
Suggested Reading
7
2 Gd82559Er Architectural Overview
9
Parallel Subsystem Overview
9
FIFO Subsystem Overview
10
10/100 Mbps Serial CSMA/CD Unit Overview
11
10/100 Mbps Physical Layer Unit
11
3 Signal Descriptions
13
Signal Type Definitions
13
PCI Bus Interface Signals
13
Address and Data Signals
13
Interface Control Signals
14
System and Power Management Signals
15
Local Memory Interface Signals
15
Testability Port Signals
16
PHY Signals
17
4 Gd82559Er Media Access Control Functional Description
19
82559ER Initialization
19
Initialization Effects on 82559ER Units
19
PCI Interface
20
82559ER Bus Operations
20
Clockrun Signal
28
Power Management Event Signal
28
Power States
29
Wake-Up Events
33
Parallel Flash Interface
34
Serial EEPROM Interface
34
10/100 Mbps CSMA/CD Unit
36
Full Duplex
37
Flow Control
37
Address Filtering Modifications
37
Long Frame Reception
37
Media Independent Interface (MII) Management Interface
38
5 Gd82559Er Test Port Functionality
39
Introduction
39
Asynchronous Test Mode
39
Test Function Description
39
Tristate
40
Nand - Tree
40
6 Gd82559Er Physical Layer Functional Description
43
100BASE-TX PHY Unit
43
100BASE-TX Transmit Clock Generation
43
100BASE-TX Transmit Blocks
43
100BASE-TX Receive Blocks
46
100BASE-TX Collision Detection
47
100BASE-TX Link Integrity and Auto-Negotiation Solution
47
Auto 10/100 Mbps Speed Selection
47
10BASE-T Functionality
47
10BASE-T Transmit Clock Generation
47
10BASE-T Transmit Blocks
48
10BASE-T Receive Blocks
48
10BASE-T Collision Detection
49
10BASE-T Link Integrity
49
10BASE-T Jabber Control Function
49
10BASE-T Full Duplex
49
Auto-Negotiation Functionality
49
Description
50
Parallel Detect and Auto-Negotiation
50
LED Description
51
7 Pci Configuration Registers
53
LAN (Ethernet) PCI Configuration Space
53
PCI Vendor ID and Device ID Registers
53
PCI Command Register
54
PCI Status Register
55
PCI Revision ID Register
56
PCI Class Code Register
56
PCI Cache Line Size Register
56
PCI Latency Timer
57
PCI Header Type
57
PCI Base Address Registers
57
PCI Subsystem Vendor ID and Subsystem ID Registers
59
Capability Pointer
59
Interrupt Line Register
59
Interrupt Pin Register
60
Minimum Grant Register
60
Maximum Latency Register
60
Capability ID Register
60
Next Item Pointer
60
Power Management Capabilities Register
60
Power Management Control/Status Register (PMCSR)
61
Data Register
62
8 Control/Status Registers
63
LAN (Ethernet) Control/Status Registers
63
System Control Block Status Word
64
System Control Block Command Word
65
System Control Block General Pointer
65
Port
65
Flash Control Register
65
EEPROM Control Register
65
Management Data Interface Control Register
65
Receive Direct Memory Access Byte Count
66
Early Receive Interrupt
66
Flow Control Register
66
Power Management Driver Register
66
General Control Register
67
General Status Register
67
Statistical Counters
68
9 Phy Unit Registers
71
MDI Registers 0 - 7
71
Register 0: Control Register Bit Definitions
71
Register 1: Status Register Bit Definitions
72
Register 2: PHY Identifier Register Bit Definitions
73
Register 3: PHY Identifier Register Bit Definitions
73
Register 4: Auto-Negotiation Advertisement Register Bit Definitions
73
Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions
73
Register 6: Auto-Negotiation Expansion Register Bit Definitions
74
MDI Registers 8 - 15
74
MDI Register 16 - 31
74
Register 16: PHY Unit Status and Control Register Bit Definitions
74
Register 17: PHY Unit Special Control Bit Definitions
75
Register 18: PHY Address Register
76
Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions
76
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
76
Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
76
Register 22: Receive Symbol Error Counter Bit Definitions
76
Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions
77
Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
77
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
77
Register 26: Equalizer Control and Status Bit Definitions
77
Register 27: PHY Unit Special Control Bit Definitions
77
10 Electrical and Timing Specifications
79
Absolute Maximum Ratings
79
DC Specifications
79
AC Specifications
82
Timing Specifications
83
Clocks Specifications
83
Timing Parameters
84
12 Package and Pinout Information
91
Package Information
91
Pinout Information
92
GD82559ER Pin Assignments
92
GD82559ER Ball Grid Array Diagram
94
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Intel GD82559ER Specifications
General
Brand
Intel
Model
GD82559ER
Category
Computer Hardware
Language
English
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