To Next PageTo Next Page
Need help?Do you have a question about the Intel GD82559ER and is the answer not in the manual?
General| Manufacturer | Intel |
|---|---|
| Model | GD82559ER |
| Category | Computer Hardware |
| Device Type | Ethernet Controller |
| Interface | PCI |
| Data Rate | 10/100 Mbps |
| Bus Type | PCI |
| Supported Standards | IEEE 802.3, IEEE 802.3u |
Highlights features like integrated PHY, glueless PCI, Flash interface, and ACPI support.
Covers chained memory, dynamic transmit chaining, full duplex, and auto-negotiation.
Details low power 3.3V device, dynamic standby, deep power down, and clockrun support.
Overview of the GD82559ER, a 10/100 Mbps Ethernet controller.
List of related Intel and industry specifications for power management and PCI.
Details the PCI bus interface, micromachine, and control/flash interfaces of the subsystem.
Explains the 3 Kbyte transmit and receive FIFOs for buffering data.
Describes the CSMA/CD unit's role in Ethernet protocols and full-duplex mode.
Covers the PHY unit's support for 10/100 Mbps, auto-negotiation, and LED indicators.
Defines input/output types like IN, OUT, Tri-State, Open Drain, etc.
Details signals related to the PCI bus, including address, data, control, and power management.
Covers signals for local memory, test ports, and physical layer interfaces, including clock and differential pairs.
Covers device initialization sources and PCI bus interaction as master/slave.
Details power states, wake-up events, Flash, EEPROM, CSMA/CD, and MII interfaces.
Access point for test data for production level testing.
Describes modes for system-level design use and validation.
Explains tests for board design, functionality, and solder integrity.
Covers test modes like 85/85, TriState, and Nand-Tree for board testing.
Details transmit/receive blocks, clock generation, collision detection, and auto-negotiation.
Covers transmit/receive blocks, clock generation, collision detection, and full duplex for 10BASE-T.
Explains auto-negotiation functionality, parallel detect, and LED indicators.
Details the 16 Dwords of Type 0 Configuration Space Header and Vendor/Device IDs.
Covers Command, Status, Revision ID, Class Code, Cache Line Size, Latency Timer, and Header Type registers.
Details Base Address Registers, Subsystem IDs, Capabilities, PMCSR, and Data Registers.
Overview of the Control/Status Register (CSR) structure and its main blocks.
Details SCB registers (Status, Command, Pointer, PORT) and interface controls (Flash, EEPROM, MDI).
Covers PMDR, General Control/Status registers, and Statistical Counters for device operation.
Control and status register definitions for MDI registers 0 through 7, including Auto-Negotiation.
Details PHY unit status, control, error, and counter registers from 16 to 31.
Lists maximum ratings and provides DC electrical characteristics for power supply and interface.
Details AC specifications for PCI signaling and driver characteristics.
Covers various timing parameters for PCI, X1, Flash, EEPROM, and PHY interfaces, including measurement conditions.
Describes the 196-pin Ball Grid Array (BGA) package and its dimensions.
Provides GD82559ER pin assignments and a ball grid array diagram for physical connection reference.
