KD-SX980
1-25
3.Pin function
Pin No. Symbol Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VIN1-A
VIN1+A
VCCP1
VO1+
VO1-
VO2+
VO2-
VO3+
VO3-
VO4+
VO4-
VCCP2
VIN4
VIN4G
VIN3
VIN3G
VIN2
VIN2G
REGIN
3.3VREG
VCCS
VREFIN
MUTE
VIN1_SW
S_GND
VIN1+B
VIN1-B
VIN1
CH1 input AMP_inverted input
CH1 input AMP_non-inverted input
CH1 and CH2 power stage power supply
Output pin(+)for channel 1
CH1 output pin (-) for channel 1
Output pin(+)for channel 2
Output pin(-)for channel 2
Output pin(+)for channel 3
Output pin(-)for channel 3
Output pin(+)for channel 4
Output pin(-)for channel 4
CH3 and CH4 power stage powr supply
Input pin for channel 4
Input pin for channel 4(for gain adjustment)
Input pin for channel 3
Input pin for channel 3(for gain adjustment)
Input pin for channel 2
Input pin for channel 2(for gain adjustment)
External PNP transistor, base connection
3.3VREG output pin, external PNP transistor,collector connection
Signal system GND
Reference voltage application pin
Output ON/OFF pin
CH1 input OP AMP_changeover pin
Signal system GND
CH1 AMP_B non-inverted input pin
CH1 AMP_B inverted input pin
CH1 input pin, input OP_AMP output pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
Symbol
A0-A16
I/O1-I/O8
CS1,CS2
WE
OE
VDD
VSS
NC
Function
Address inputs
Data inpts/outputs
Chip select input
Write enable input
Output enable input
Power supply
Ground
No connection
W24L010AJ-AS-X (IC653) : SRAM
VDD
VSS
A0
A16
CS2
CS1
OE
WE
I/O1
I/O8
DECODER
CONTROL
CORE
ARRAY
DATA I/O
1.Pin layout 2.Block diagram 3.Pin functions
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
To Next Page
Loading...
Need help?
General
