JVC MX-G50 - Page 41

MX-G50/MX-G56
1-41
2.Block diagram
Interrupt Control
A15-A0
D7-D0
TA
CE
OE
DASEC
Standby Control
Clock
Generator
CF
RC
X’tal
Base Time
r
SIO0
SIO1
Timer 0
Tim
er 1
ADC
INT0-3
Noise Filter
SIO Auto
matic
transmission
RAM
128 by
te
s
VFD
Controller
High voltage Output
Bus Interface
Port 1
Port 3
Port 7
Port 8
IR PLA
PROM
Control
PROM(48KB)
PC
ACC
B Register
C Register
A
LU
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog Timer