LAPIS Semiconductor EASE1000 - Recommended Circuitry Using TEST1_N Pin and TEST0 Pin

EASE1000 User’s Manual
Chapter 2 General Description
2.5.1.2.2 Recommended circuitry using TEST1_N pin and TEST0 pin
The example of a circuit connected with EASE1000 using TEST1_N pin and TEST0 pin is shown below.
- Do not connect any parts to TEST1_N pin and TEST0 pin.
- EASE1000 controls reset of a target LSI, do not reset from a RESET_N pin during debugging.
EASE1000
Interface connector
VTref
RST_OUT/SCK
1
5
SDATA
7
3.3VOUT
13
NC
Vss
2,4,6,8,10,12
3,11,14
~
V DD
TEST1_N
TEST0
Vss
Target LSI
VDDL
9
VDDL
RESET_N
Figure 2-6
Recommended circuitry using TEST1_N pin and TEST0 pin
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