CrossLink Programming and Configuration Usage Guide
Technical Note
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-TN-02014-1.2
During the initial stages of device configuration, the frequency value specified using MCCLK_FREQ is loaded into the
FPGA. When CrossLink accepts the new MCCLK_FREQ value, the MCK output begins driving the selected frequency.
Make sure when selecting the MCCLK_FREQ that you do not exceed the frequency specification of your configuration
memory, or of your PCB. Refer to the CrossLink AC specifications in the CrossLink Family Data Sheet (FPGA-DS-02007)
when making MCCLK_FREQ decisions.
SPI_SS
The SPI_SS pin is the Slave SPI ports chip select. An external SPI bus master asserts the SPI_SS pin active LOW in order
to perform actions using CrossLink’s programming and Configuration Logic. The SPI_SS pin is available when CrossLink
is in the Feature Row HW Default Mode state, and in User Mode when the Slave SPI port is set to the ENABLE setting.
The SPI_SS pin is a general purpose I/O in User Mode when the Slave SPI port is set to the DISABLE setting.
Proper operation of the CrossLink device depends upon maintaining the SPI_SS pin in the correct state:
SPI_SS must be deasserted (that is, held High) when configuring using Master SPI mode. SPI_SS signal needs to be
clean during power up. Noise on SPI_SS pins may cause device failing to download from flash. SPI_SS must be
asserted when configuring using Slave SPI mode.
SPI_SS must be deasserted when CrossLink is in User Mode, and SPI memory transactions are initiated using the
internal WISHBONE bus.
The Master SPI port and the Slave SPI port share three common pins, MOSI, MISO, and MCK/SPI_SS. They are
not permitted to be accessed at the same time. In Diamond, if both the ports are enabled at the same time,
the flow fails.
SPI_SS must be deasserted (even if recovered for GPIO) whenever the Feature Row is erased via I
2
C sysConfig port
(for example embedded reconfiguration). If asserted, configuration may not complete successfully.
Lattice recommends the SPI_SS pin to be pulled high externally to augment the weak internal pull-up.
In case of CrossLink, the SPI_SS pin is shared with I
2
C SCL line. The startup sequence for
CrossLink decides Slave SPI and Slave I
2
C pins while the device is in configuration mode.
The Startup state machine determines if either the I
2
C or the SPI slave mode is
activated, and if so, identifies which one is activated. When one is activated, the other is
locked out until the next refresh event or power cycle and so are its concerned pins.
CSN
The CSN pin is an active LOW chip select used by the Master SPI configuration mode to enable an external SPI Flash.
When CrossLink is programmed to configure in either External or Dual Boot mode, the CSN pin is asserted to the
attached SPI Flash. CrossLink asserts CSN until all configuration data bytes have been loaded, at which time the MCK
enters a high impedance state.
When CrossLink is in the Feature Row HW Default Mode state, the CSN is SPI_SS with a weak pullup. It must have an
external pullup resistor when the External and Dual Boot configuration modes are used. MCK must ramp in tandem
with the SPI PROM VCC input. It remains SPI_SS when the FPGA enters User Mode in software default state. You must
ENABLE the Master SPI port to reserve CSN for use by the internal SPI Master logic.
When configuring from an external SPI Flash, ensure that the SPI Flash VCC and the CrossLink VCCIO0 are at the same
level. Ensure that the SPI Flash VCC is at the recommended operating level.
Some SPI PROM manufacturers require the chip select input of the PROM ramp in unison to the PROMs VCC rail. The
CSN pin, by default, has a weak pull-up resistor internally. Adding a 4.7 kΩ to 10 kΩ pull-up resistor to the CSSPIN pin
on CrossLink is recommended.
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