CrossLink Programming and Configuration Usage Guide
Technical Note
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CONFIG_SECURE
When this preference is set to ON, the read-back of the SRAM memory or the NVCM are blocked. The CrossLink device
cannot be read back. The CONFIG_SECURE fuse and the NVCM are erased in tandem. When the security fuses are
reset, the device can be reprogrammed. This depends on the target block (SRAM or NVCM). CONFIG_SECURE only
prevents readback for the targeted block.
ONE_TIME_PROGRAM
CrossLink has One Time Programmable (OTP) fuses that can be used to prevent the SRAM from being erased or
programmed.
7. Device Wake-up Sequence
When configuration is completed (the SRAM is loaded), the device wakes up in a predictable fashion. If the CrossLink
device is the only or the last device in the chain, the Wake-up process begins when configuration is completed and the
internal DONE bit is set. Upstream sources should not enable its output until CrossLink has completed its configuration
to ensure that CrossLink is operating in a known state.
7.1. Wake-up Signals
Three internal signals, GSR, GWDIS, and GOE, determine the Wake-up sequence.
GSR is used to set and reset the core of the device. GSR is asserted (LOW) during configuration and de-asserted
(high) in the Wake-up sequence.
When the GWDIS signal is LOW, it safeguards the integrity of the RAM Blocks and LUTs in the device. This signal is
LOW before the device wakes up. This control signal does not control the primary input pin to the device but
controls specific control ports of EBR and LUTs.
When LOW, GOE prevents the device’s I/O buffers from driving the pins. The GOE only controls output pins. When
the internal DONE is asserted CrossLink responds to input data.
When high, the CDONE pin indicates that configuration is complete and that no errors are detected.
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