Lattice Semiconductor CrossLink User Manual

CrossLink Programming and Configuration Usage Guide
Technical Note
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 FPGA-TN-02014-1.2
References
For more information, refer to the following documents:
 CrossLink Family Data Sheet (FPGA-DS-02007)
 CrossLink High-Speed I/O Interface (FPGA-TN-02012)
 CrossLink Hardware Checklist (FPGA-TN-02013)
 CrossLink sysCLOCK PLL/DLL Design and Usage Guide (FPGA-TN02015)
 CrossLink sysI/O Usage Guide (FPGA-TN-02016)
 CrossLink Memory Usage Guide (FPGA-TN-02017)
 Power Management and Calculation for CrossLink Devices (FPGA-TN-02018)
 CrossLink I2C Hardened IP Usage Guide (FPGA-TN02019)
 Advanced CrossLink I2C Hardened IP Reference Guide (FPGA-TN02020)
 Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
 Programming Tools User Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
Revision History
Date
Version
Change Summary
December 2017
1.2
 Updated the Configuration Process and Flow section. Removed references to
Table 4.1.
 Updated the Power-up Sequence section
 Added information on upstream sources
 Changed V
CCAUX25VPP
to V
CCAUX
 Updated the Initialization section
 Updated the Configuration Ports Default Behavior and Arbitration section
 Changed “toggle LOW or REFRESH” to “toggle from LOW to HIGH or
REFRESH”
 Added information on the Activation Key
 Updated the Configuration section. Added information on the Activation Key
 Updated the Clearing the Configuration Memory and Re-initialization section.
Added content to the third method of clearing the internal configuration
memory
 Updated the Self-Download Port Pins section. Revised the first and last
paragraphs.
 Updated the Master and Slave SPI Configuration Port Pins section. Updated the
CRESET_B direction and description in Table 4.5. Master SPI Configuration Port
Pins and Table 4.6. Slave SPI Configuration Port Pins
 Updated the last paragraph in SDM Mode section
 Updated the Master SPI Configuration Mode section.
 Updated configuration data flow in the fourth paragraph
 Updated SPI Flash configuration information in the last paragraph
 Added information on the Activation Key to the Slave SPI Mode section
 Added information on the Activation Key to the I2C Configuration Mode section
 Updated introductory paragraph of the Device Wake-up Sequence section

Lattice Semiconductor CrossLink Specifications

General

Brand	Lattice Semiconductor
Model	CrossLink
Category	Controller
Language	English