Lattice Semiconductor CrossLink - Page 3

CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2 3
Figures
Figure 4.1. Configuration Flow ............................................................................................................................................. 7
Figure 4.2. Period CRESETB is Always Observed ................................................................................................................. 11
Figure 4.3. Configuration from CRESETB Timing................................................................................................................. 12
Figure 4.4. Configuration Error Notification ....................................................................................................................... 12
Figure 5.1. Slave SPI Configuration Mode........................................................................................................................... 19
Figure 5.2. I
2
C Configuration Logic ...................................................................................................................................... 20
Figure 5.3. Bitstream Update Using TransFR ...................................................................................................................... 21
Figure 5.4. Example Process Flow ....................................................................................................................................... 22
Figure 6.1. sysCONFIG Preferences in Global Preferences Tab, Diamond Spreadsheet View ............................................ 23
Tables
Table 4.1. Slave Configuration Port Activation Key .............................................................................................................. 8
Table 4.2. Maximum Configuration Bits ............................................................................................................................. 10
Table 4.3. Default State of sysCONFIG Pins ........................................................................................................................ 11
Table 4.4. Default State in Diamond for each Port ............................................................................................................. 11
Table 4.5. Master SPI Configuration Port Pins .................................................................................................................... 13
Table 4.6. Slave SPI Configuration Port Pins ....................................................................................................................... 13
Table 5.1. Master SPI Configuration Port Pins .................................................................................................................... 16
Table 5.2. Master SPI Configuration Software Settings ...................................................................................................... 17
Table 5.3. Dual-Boot Configuration Settings ...................................................................................................................... 18
Table 5.4. Slave SPI Port Pins .............................................................................................................................................. 18
Table 5.5. I
2
C Port Pins ........................................................................................................................................................ 19
Table 5.6. Slave Addresses for I
2
C Ports ............................................................................................................................. 20
Table 6.1. Configuration Mode/Port Options ..................................................................................................................... 24
Table 6.2. Configuration Mode/Port Options ..................................................................................................................... 26