Do you have a question about the Lattice MIPI D-PHY and is the answer not in the manual?
Details common display resolutions and their pixel clock calculation.
Defines color depth in bits-per-pixel and bits-per-component.
Explains lane scalability for increased bandwidth and lower clock rates.
Formulas for calculating pixel clock, total data rate, and per-lane data rate.
Illustrates bandwidth and data rate calculations with practical examples.
Compares MIPI D-PHY hardware features across Lattice FPGA families.
Details MIPI receiver interface calculations for various FPGA families.
Details MIPI transmitter interface calculations for various FPGA families.
Matrix for selecting MIPI D-PHY lane number and line rate based on video format.