Lattice MIPI D-PHY - Default Chapter; Table of Contents

MIPI D-PHY Bandwidth Matrix Table
User Guide
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2 FPGA-UG-02041-1.1
Contents
Acronyms in This Document .......................................................................................................................................... 4
1. Introduction .......................................................................................................................................................... 5
2. Video Format ......................................................................................................................................................... 6
2.1. Video Resolution and Pixel Clock .................................................................................................................. 7
2.2. Color Depth .................................................................................................................................................. 8
3. MIPI CSI-2/DSI Interfaces ....................................................................................................................................... 9
4. Packetizing .......................................................................................................................................................... 13
4.1. xMulti-lane ................................................................................................................................................. 14
5. Bandwidth and Data Rate .................................................................................................................................... 15
5.1. Bandwidth and Data Rate Calculation ......................................................................................................... 15
5.1.1. Pixel Clock .............................................................................................................................................. 15
5.1.2. Total Data Rate or Bandwidth ................................................................................................................. 15
5.1.3. Data Rate per Lane ................................................................................................................................. 15
5.1.4. Bit Clock ................................................................................................................................................. 15
5.2. Examples .................................................................................................................................................... 15
5.2.1. Example 1: 1920x1080p@60Hz, RAW10, 2-lane ...................................................................................... 15
5.2.2. Example 2: 3840x2160@30Hz, RAW8, 4-lane .......................................................................................... 15
6. Device Selection .................................................................................................................................................. 16
6.1. Hardware Features ..................................................................................................................................... 16
7. MIPI Data Rate Calculation .................................................................................................................................. 18
7.1. FPGA Receiver Interface ............................................................................................................................. 18
7.1.1. MachXO2/MachXO3L ............................................................................................................................. 18
7.1.2. LatticeECP3 ............................................................................................................................................ 19
7.1.3. ECP5/ECP5-5G ........................................................................................................................................ 20
7.1.4. CrossLink Soft D-PHY .............................................................................................................................. 21
7.1.5. t
SU
/t
HD
Valid Window at Higher Data Rate ............................................................................................... 21
7.2. FPGA Transmitter Interface ........................................................................................................................ 22
7.2.1. MachXO2/MachXO3L ............................................................................................................................. 22
7.2.2. LatticeECP3 ............................................................................................................................................ 23
7.2.3. ECP5/ECP5-5G ........................................................................................................................................ 24
7.2.4. Tskew Window at Higher Data Rate ........................................................................................................ 24
7.3. MIPI D-PHY Lane Number Selection Matrix Table ........................................................................................ 25
Reference ................................................................................................................................................................... 27
Technical Support ....................................................................................................................................................... 27
Revision History .......................................................................................................................................................... 27