Lattice MIPI D-PHY - Page 3

MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1 3
Figures
Figure 1.1. CMOS Sensor Bridge Model .......................................................................................................................... 5
Figure 2.1. Interlaced Mode Video Frame Format .......................................................................................................... 6
Figure 2.2. Most Common Display Resolutions ............................................................................................................... 7
Figure 3.1. Unidirectional Receive HS Mode and Bidirectional LP Mode Interface Implementation ................................. 9
Figure 3.2. Unidirectional Receive HS Mode Only Implementation ............................................................................... 10
Figure 3.3. Unidirectional Transmit HS Mode and Bidirectional LP Mode Interface Implementation ............................. 11
Figure 3.4. Unidirectional Transmit HS Mode Only Implementation ............................................................................. 12
Figure 4.1. An Example of RAW10 Transmissions on CSI-2 Bus ..................................................................................... 13
Figure 7.1. MachXO2/MachXO3L Maximum Data Rate ................................................................................................. 18
Figure 7.2. LatticeECP3 Maximum Data Rate ................................................................................................................ 19
Figure 7.3. ECP5/ECP5-5G Maximum Data Rate ........................................................................................................... 20
Figure 7.4. CrossLink Maximum Data Rate ................................................................................................................... 21
Figure 7.5. MachXO2 Maximum Data Rate ................................................................................................................... 22
Figure 7.6. LatticeECP3 Maximum Data Rate ................................................................................................................ 23
Figure 7.7. ECP5/ECP5-5G Maximum Data Rate ........................................................................................................... 24
Tables
Table 2.1. Common Video Format .................................................................................................................................. 8
Table 4.1. CSI-2 Packet Size Constraints* ..................................................................................................................... 14
Table 6.1. MIPI Soft D-PHY RX/TX Hardware Comparison ............................................................................................. 16
Table 7.1. t
SU
/t
HD
Window for Higher Data Rate ........................................................................................................... 21
Table 7.2. Tskew Window for Higher Data Rate ............................................................................................................ 24
Table 7.3. MIPI D-PHY Interface Lane Number and Line Rate Selection Example Matrix Table....................................... 25