Lattice MIPI D-PHY - Latticeecp3; Figure 7.6. Latticeecp3 Maximum Data Rate

MIPI D-PHY Bandwidth Matrix Table
User Guide
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FPGA-UG-02041-1.1 23
7.2.2. LatticeECP3
Maximum MIPI compliance data rate calculation for LatticeECP3:
 0.215 = 0.15 x UI
 UI = 0.215/0.15 = 1.433 ns
 Max Data Rate = 1/UI = 1/1.433 = 698 Mbps (at 0.15 UI)
Setup Time
Hold Time
0.285
0.285
At 1000 Mbps, ½ UI = 0.5
Tskew = 0.5 - 0.285 = 0.215
LatticeECP3 Data Sheet Rev. 2.8EA at 1000 Mbps
Generic DDRX2 Output with Clock and Data (>10 Bits Wide) Centered at Pin Using PLL (GDDRX2_TX.PLL.Centered)
t
DVBGDDR
f
DVAGDDR
Data Valid After CLK
f
MAX_GDDR
DDRX2 Clock Frequency
285
—
500
285
—
— 370
—
420
370
—
— 431
—
375
432
—
—
ps
MHz
ps
Data Valid Before CLK All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices
Left and Right Sides
Figure 7.6. LatticeECP3 Maximum Data Rate