4-8 Theory of Operation
Bus Error Generation
The MPC603e expects NTA and NAACK signals for acknowledgement to the current
bus cycle, and inserts wait states during the period NTA and NAACK are kept at
“high” levels (any of external devices have not pulled these signals "low"). As long
as any of the devices do not return the acknowledgement, the bus is kept in this
wait-condition. An external circuit is then required to generate a bus-error signal to
break the pending cycle after a given time-out. The bus error is generated by pulling
the NTEA pin of the CPU down to “low”. This job is done by the BUS (IC93) which
counts the number of wait-states that have already passed through the counter.
With this operation, the system can successfully force the termination of the current
cycle. Some devices, such as the VGA video controller, have their own logic to
generate a bus error. Therefore, any access operations for those devices do not
need this circuit.
GPIB Interface
GP-IB controller is the National Instrument’s NAT4882. It has NEC-7210 software
compatible made and it includes bus drivers.
Internal Printer Interface
Printer control is the same as for the normal Centronics interface. This circuit
consists of buffers only.
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