4-4 Theory of Operation
Memory Mapping
When power is turned on, the internal software automatically sets the system's
memory size to the largest capacity available with the DIMM that is installed (64MB -
512MB DIMM size).
VGA controller
The VGA controller chip 65545(IC29) contains the logic circuits to decode its own
addresses. It generates all the video signals (RGB, H/V, and all control lines to drive
the flat panel), and controls its associated 1 MB video DRAM (to read, write and
refresh). There are two 2Mb video DRAMs mounted but only 512KB of each of the
DRAM's is used.
All timings are extracted from the 16MHz bus clock; therefore, no external crystal or
time-base is required. The horizontal and vertical synchronization signals are sent
to the external video connector (a half pitch, D-SUB15 pin connector is used).
The 65545 chip can support several bus interfaces (PCI, ISA, VL, etc), the system
employs it for VL-bus applications with the mode of 256-color palette operations.
The controller has an 18bit color palette and can display 256 colors out of the
available 260,000.
The power supply circuit for the liquid crystal panel has a MOSFET switch that
switches the power supply of LCD to 3.3V or 5V.
Also the VGA controller has a switch, it switches the max signal level for the LCD to
3.3V or 5V.
Super-I/O
This device controls RS-232C, floppy disk, and parallel port operations. The
controller has its own time-base with a 24MHz crystal. RS-232C can be used by
simply connecting the MAX232 buffer (IC31) to it. Since the Super I/O chip has a
16-byte buffer, high speed data transfer is easily carried out.
A 2HD disk drive can be directly connected to the system without any external
components other than a pull-up resistor; it can be operated in interruption mode.
The parallel interface is also activated without other external components other than
a pull-up resistor, for the use of 2-way communication.
Bus Control
The BUS (IC93) performs all bus cycles except those for SDRAM. When the bus
cycle starts, the MPC603e must terminate the bus cycle by returning signals after
acknowledging each of the data and addresses, from the outside. The BUS is used
to generate the acknowledgement signals.
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