LeCroy Waverunner2 Series User Manual

Relation of I/O Structure to the associated CPLDs
The following block-diagram describes the flow in the decoder and the relationships
between the acknowledgement to be returned to the CPU and CPLDs.
Three-line boxes are CPLDs, and one-line boxes indicate other ICs and function
blocks.
• SDM does all the controls for the access of the SDRAM (Initialize memory,
Decode and Mapping, Read/Write, Burst Read/Write, Refresh).
• Bus controls is the bus cycle of the entire CPU board. (Decode all areas other
than SDRAM, Read/Write of 32bits bus, Read/Write of the bus via bus sizer,
detection of bus error).
VG
A
Su
pp
er MAIN SDRAM
MUX
CPU BUS
Select
To CPU
BUS
Select
Select
Select Ack
SD
Ack
Ack
Decoder
Buffe
Wait
Wait
Address
8/16bit
Select
71059
GP-IB (16bit)
NVRAM
RTC
Small Peripherals
Front Panel
Flash ROM
PCMCIA (16bit)
Data
CPU BUS (Data)
Buffe
BUS sizer
Figure 4-2 I/O Structure
Theory of Operation 4-9

LeCroy Waverunner2 Series Specifications

General

Brand	LeCroy
Model	Waverunner2 Series
Category	Test Equipment
Language	English