MPX G2 Service Manual
6-18
performs a synchronization. When this is completed, the 2186 will own the bus about 30% of time, starting
just after the rising edge of FS (located above U15). Power-up is complete.
FPGA Serial Communications
The serial data is clocked to/from the A/D and D/A converters at 128FS. A quadrature word clock
(FS_QUAD) allows muxing four channels of A/D and D/A into a single serial port. All A/D and D/A data is in
I
2
S format, meaning MSB-first, starting one bit cell after the rising or falling edge of the converter's word
clock.
The serial link between the 2186 and the Lexichip is broken into 128 time slots organized as 8 bidirectional
channels of 16-bit data:
TIME SLOT DSP_LEX_DATA LEX_DSP_DATA
----------------------------------------------------------------------------------------------------------------------
9-24 RIGHT REVERB RIGHT REVERB
25-40 LEFT DELAY LEFT DELAY 1
41-56 RIGHT DELAY LEFT DELAY 2
57-72 LEFT DELAY 3
73-88 RIGHT DELAY 1
89-104 RIGHT DELAY 2
105-120 RIGHT DELAY 3
121-8 LEFT REVERB LEFT REVERB
To Next Page
Loading...
Need help?
General
