LG HT353SD - Page 44

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Only for training and service purposes
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2-35
• BLOCK DIAGRAM
Interrupt control
Standby
control
IR PLA
Bus interface
Port 0
Port 1
SIO
0
SIO
1
Timer 0
Timer 1
Timer 4
Timer 5
Port 2
Port 7
Port 8
ADC
ALU
Flash ROM
PC
ACC
B register
C register
PSW
RAR
RAM
Stack pointer
Watchdog timer
CF
RC
X’tal
MRC
Clock
generato
r
UART2
On-chip Debugger
ROM correct
PWM2/3
UART1
Base timer
Port C
Timer 6
INT0 to INT7
Noise filter
Port 3
Timer 7