Marantz 2240 - MPX Stereo Decoding Circuit

The
transistor
H317,
also,
turns
off
when
transistor
H309
or
H311
turns
on,
and
turns
on
the
transistor
H303
connected
to
pin
8
of
the
MPX
stereo
decoding
IC.
Pin
8
is
therefore
grounded
equivalently
to
set
the
IC
in
the
monaural
mode
of
operation.
This
prevent
misoperation
due
to
undesirable
noises
when
the
FM
tuner
is
out
of
tuning.
The
third
input
is
obtained
from
the
FM
discriminator
circuit.
The
DC
output
so
called
“s"
curve
is
applied
to
the
gate
of
H312
through
a
resistor
R273
and
dividing
network
(R361
&
R362).
The
DC
output
is
zero
with
a
station
correctly
tuned
in,
but
wil!
vary
from
negative
to
positive
values
or
vice
versa
when
the
tuning
point
is
deviated
toward
either
plus
or
minus
frequency
from
the correct
tuning
frequency.
When
the
DC
output
is
increased
to
a
greater
level
than
that
of
predetermined,
the
increased
source
potential
of
H312
makes
the
transistor
H315
turn
on
(this
means
the
collector
of
H309
is
short-circuited
to
the
ground)
...
H301
turn
off,
...
H317
turn
off
...
H303
turn
on
(This
grounds
pin
8
of
the
MPX
stereo
decoding
IC,
therefore
the
decoder
is
set
in
the
monaural
mode
of
operation
and
the
stereo
indicator
lamp
turns
off).
When
the
DC
output
is
increased
to
the
negative
predetermined
level,
the
decreased
source
potential
turns
off
the
H313
which
in
turn
makes
the
H314
turn
on
(this
means
the
collector
of
H309
is
short-circuited
to
the
ground).
The
subsequent
changes
are
exactly
the
same
as
that
just
described
above.
Thus
when
the
tuning
is
shifted-or-deviated
to
the
certain
frequencies
in
which
undesirable
noisy
side-audio
signals
are
produced,
both
muting
and
MONAU
RAL/STEREO
switching
transistors
H303
are
operated
automatically
and
open
the
circuits.
With
the
station
correctly
tuned
in,
the
bias
current
of
the
FET
H312
is
adjusted
so
that
both
transistor
H314
and
H315
are
not
turned
on,
giving
no
effect
on
the
transistor
H308.
3.2 MPX Stereo Decoding Circuit
The
stereo
composite
signal
from
the
buffer
amplifier
undergoes
a
phase
compensation
by
R301
and
C301,
is
applied
through
the
muting
switching
FET
H301
to
the
input
terminal,
pin
2,
of
the
MPX
stereo
decoding
1C
H321
on
a
PLL
(Phase
Locked
Loop)
basis,
and
decoded
into
the
left
and
right
stereo
signals,
which
become
available
at
pins
4
and
5
respectively.
These
decoded
left
and
right
stereo
audio
signals
are
introduced
through
a
low
pass
filter
composed
of
L301
to
L304
and
C311
to
C320
for
elimination.
of
undesirable
residual
switching
signal
and
through
a
de-emphasis
network
consisting
of
R325,
R326,
C321
and
C322,
into
the
npn-pnp
direct
coupled
audio
amplifier,
where
the
signals
are
amplified
to
a
required
level
for
the
output
from
J311
and
J313.
From
these
jacks,
the
audio
signals
are
led
to
the
TAPE
OUTPUT
jacks
through
the
function
switch.
Figure
1
presents
an
internal
block
diagram
showing
the
functions
of
the
PLL
basis
MPX
stereo
decoding
IC
HA1156.
The
input
stereo
composite
signal,
amplified
by
the
audio
amplifier,
is
delivered
to
the
phase
detectors
PD-1
and
PD-2.
A
part
of
the
stereo
composite
signal
is
also
applied
to
the
stereo
decoder
section.
The
VCO
(Voltage
Control
Oscillator)
produces
a
free
run
oscillation
in
the
neighborhood
of
76
KHz
with
the
time
constant
determined
by
a
capacitor
C305
and
resistors
R311
and
R312
set
on
the
outside
of
pin
14.
The
VCO
output
has
its
frequency
divided
into
10
KHz
through
the
two
stages
of
the
frequency
divider
(DIV-1
&
DIV-2),
and
is
reverted
to
the
phase
detector
PD-1,
which
contains
two
input
terminals
designed
to
produce
an
output
in
proportion
to
the
product
of
the
two
input
signals.
The
signal
applied
to
one
of
the
inputs
of
PD-1
is
the
19
KHz
square
wave
formed
through
frequency
division
of
the
76
KHz
VCO
output
signal
by
the
two
stages
of
the
frequency
divider
DIV-1
and
DIV-2,
and
the
19
KHz
pilot
signal
included
in
the
stereo
composite
signal
as
a
reference
signal
is
applied
to
the
other
input.
Therefore,
the
output
of
PD-1
which
has
passed
through
the
low
pass
filter
LPF-1
provides
DC
output
voltage
in
proportion
to
the
phase
variance
between
the
two
inputs.
This
DC
output
voltage
is
amplified
by
the
DC
amplifier,
and
supplied
to
the
76
KHz
VCO
asa
control
voltage.
This
means
that
the
output
frequency
and
phase
of
the
VCO
have
been
phase-locked
to
the
input
pilot
signal.
The
38
KHz
sub-carrier
reproduced
by
PLL
as
stated
above
is
delivered
through
the
stereo
switch
to
the
stereo
decoder
seciton
as
a
switching
signal,
thus
driving
the
decoder
section.
One
of
the