SYMBOL PIN DESCRIPTION
DGND 1 0 V digital supply
V
DDD
2 5 V digital supply for both channels
IN R 3 serial one-bit data input for the right channel
n.c. 4 pin not connected; should preferably be connected to digital ground
CLK R 5 clock input for the right channel
V
DDD R
6 5 V digital supply for the right channel; this voltage determines the internal logic HIGH level
in the right channel
V
SSD R
7 −3.5 V digital supply for the right channel; this voltage determines the internal logic LOW
level in the right channel
V
ref R
8 −4 V reference voltage for the right channel switched capacitor DAC
AGND DAC R 9 0 V reference voltage for the right channel switched capacitor DAC; this pin should be
connected to analog ground
−DAC R 10 output from the right negative switched capacitor DAC; feedback connection for the right
negative operational amplifier
+DAC R 11 output from the right positive switched capacitor DAC; feedback connection for the right
positive operational amplifier
AGND R 12 0 V reference voltage for both right channel operational amplifiers
n.c. 13 pin not connected; should preferably be connected to analog ground
+OUT R 14 + output of the switched capacitor operational amplifier
−OUT R 15 − output of the switched capacitor operational amplifier
V
SSA
16 −5 V analog supply
V
DDA
17 5 V analog supply
−OUT L 18 − output of the switched capacitor operational amplifier
+OUT L 19 + output of the switched capacitor operational amplifier
n.c. 20 pin not connected; should preferably be connected to analog ground
AGND L 21 0 V reference voltage for both left channel operational amplifiers
+DAC L 22 output from the left positive switched capacitor DAC; feedback connection for the left
positive operational amplifier
−DAC L 23 output from the left negative switched capacitor DAC; feedback connection for left negative
operational amplifier
AGND DAC L 24 0 V reference voltage for the left channel switched capacitor DAC; this pin should be
connected to analog ground
V
ref L
25 −4 V reference voltage for the left channel switched capacitor DAC
V
SSD L
26 −3.5 V digital supply for the left channel; this voltage determines the internal logic LOW level
in the left channel
V
DDD L
27 5 V digital supply for the left channel; this voltage determines the internal logic HIGH level in
the left channel
CLK L 28 clock input for the left channel
n.c. 29 pin not connected; should preferably be connected to digital ground
IN L 30 serial one-bit data input for the left channel
V
SSD
31 −5 V digital supply for both channels
V
SUB
32 −5 V substrate voltage
QD01 : TDA1547
1-20
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