2-25 2-26
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (2/3)
44 TRO Output Tracking equalizer output terminal
45 VREF - Analog reference power terminal
46* RFGC Output Outputs 3-pole PWM signal of RF amplitude adjusting signal output terminal.
(PWM carrier = 88.2 kHz)
47 TEBC Output Outputs 3-pole PWM signal of tracking balance control signal output terminal.
(PWM carrier = 88.2 kHz)
48 FMO Output Outputs 3-pole PWM signal of feed equalizer output terminal.
(PWM carrier = 88.2 kHz)
49* FVO Output Outputs speed error signal or 3-pole PWM signal of feed search EQ output terminal.
(PWM carrier = 88.2 kHz)
50 DMO Output To output PWM signals of 3 poles of disc equalizer output terminal.
(PWM carrier = DPS 88.2 kHz, synchronizing with PXO)
51 2VREF - Reference power terminal
52 SEL Output Laser diode control signal
53 FLGA Output FLG-A output terminal
54 FLGB Output FLG-B output terminal
55* FLGC Output FLG-C output terminal
56 FLGD Output FLG-D output terminal
57 VDD - Power terminal
58 VSS - Connected to GND.
59-62 IO0-IO3 Input/Output General-purpose I/O port
(60*) Can be switched to input/output port possible according to commands.
In case of input port: can read terminal condition (H/L) by read commands possible.
In case of output port: can control terminal condition (H/L/HiZ) by commands possible.
63 /DMOUT Input Terminal for setting the mode outputting feed equalizer binary PWM from IO0 and 1
terminals and disc equalizer binary PWM from IO2 and 3 terminals. "L": active.
64 /CKSE - X'tal select terminal. In case of 16.9344MHz: "H"; in case of 33.8688 MHz: "L"
65* /DACT - Test terminal
66 TESIN Input Test input terminal
67 TESIO1 Input/Output Test input/output terminal
68 VSS - Digital ground terminal
69 PXI Input DSP system clock oscillation circuit input terminal
70 PXO Output DSP system clock oscillation circuit output terminal
71 VDD - Digital + power terminal
72 XVSS - Ground terminal for system clock oscillation circuit
73 XI Input System clock oscillation circuit input terminal
74* XO Output System clock oscillation circuit output terminal
75 XVDD - + power terminal for system clock oscillation circuit
76 DVDD - D/A conversion section power terminal
77* RO Output Channel R data normal rotation output terminal
78 DVSS - D/A conversion section analog ground terminal
79 DVR - D/A conversion section reference voltage terminal
80* LO Output Channel L data normal rotation output terminal
81 DVDD - D/A conversion section power terminal
82 TEST1 Input Test terminal
Pull-up
Normally open
resistor built in
83 TEST2 Input Test terminal
Pull-up
Normally open
resistor built in
84 TEST3 Input Test terminal
Pull-up
Normally open
resistor built in
85 BUS0 Input/Output Data input/output terminal for microcomputer interface Schmitt input
86 BUS1 Input/Output CMOS port
87 BUS2 Input/Output
88 BUS3 Input/Output
Pin No.
Terminal
Name
Input/Output Function
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (3/3)
89 VDD - Digital + power terminal
90 VSS - Digital ground terminal
91 BUCK Input Clock input terminal for microcomputer interface Schmitt input
92 /CCE Input Chip enable signal input terminal for microcomputer interface Schmitt input
"L": BUS0 to 3 are active.
93 TEST4 Input Test terminal
Pull-up
Normally open
resistor built in
94 /TSMOD Input Local test mode select terminal
Pull-up
resistor built in
95 /RST Input Reset signal input terminal
Pull-up
"L" in case of reset
resistor built in
Pull-up resistor
96 TEST0 Input Test terminal
Pull-up
Normally open
resistor built in
Pull-up resistor
97* /HSO Output Playback speed mode flag output terminal
98* /UHSO Output
99 EMPH Output Emphasis flag output terminal for sub-code Q data
H: emphasis ON, L: emphasis OFF
Output polarity can be inverted according to commands
100 LRCK Output Channel clock (44.1 kHz) output terminal
L channel: L, R channel: H
Output polarity can be inverted according to commands
Pin No.
Terminal
Name
Input/Output Function
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
/UHSO
H H Normal speed playback
H L Double speed playback
L H 4-time speed playback
L L 8-time speed playback
/HSO
Playback speed
76DVDD
77RO
78DVSS
79DVR
80LO
81DVDD
82TEST1
83TEST2
84TEST3
85BUS0
86BUS1
87BUS2
88BUS3
89VDD
90VSS
91BUCK
92/CCE
93TEST4
94/TSMOD
95/RST
96TEST0
97/HSO
98/UHSO
99EMPH
100LRCX
50
DMO
49 FVO
48 FMO
47
TEBC
46
RFGC
45
VREF
44
TRO
43 FOO
42
TEZI
41 TEI
40 TSIN
39 SBAD
38 FEI
37 RFRP
36 RFZI
35
RFCT
34 AVDD
33
RFI
32
SLCO
31 AVSS
30 VCOF
29 VCOREF
28 PVREF
27 LPFO
26 LPFN
1234
VSS
BCK
AOUT
5678
MBOV
IPF
SBOK
CLCK
91011
12
VDD
VSS
DATA
13
SBSY
14
SPCK
15
SPDA
16
COFS
17
MDNIT
18
VDD
19
TESIOO
20
P2VREF
21
SPDO
22
PDOS
23
PDO
24
TMAXS
25
TMAX
SFSY
DOUT
75 74 73 72
XVDD
XO
XI
71
70
69
68
VDD
PXO
PXI
VSS
67
66
65
64
TESIO1
TESIN
/DACT
63
/DMOUT
62
IO3
61
IO2
60
IO1
59
IO0
58
VSS
57
VDD
56
FLGD
55
FLGC
54
FLGB
53
FLGA
52
SEL
51
2VREF
/CKSE
XVSS
LPF
1BIT
DAC
CLOCK
GENERATOR
1 Gk RAM
CLV SERVO
RAM
ROM
DIGITAL
EQUALIZER
SERVO
CONTROL
PWM
D/A
A/D
+
-
+
-
+
-
+
-
PWM
VCO
PLL TMAX
MICROCONPUTER
INTERFACE
ADDRESS
CIRCUIT AUTOMATIC
CONTROL
CIRCUIT
CORRECTION
CIRCUIT
EFM DEMODULATION
TO PROTECT
SYNCHRONIZING
SIGNAL
DATA
SLICER
AUDIO
OUTPUT
CIRCUIT
DIGITAL OUT
SUB-CODE
DEMODULATION
CIRCUIT
STATUS
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