Marantz UD9004/U1B - Page 57

55
UD9004
ADV7344BSTZ Pin Function
Pin No. Mnemonic
Input/
Output
Description
13, 12,
9 to 2
Y9 to Y0 I 10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to
Table 31 for input modes.
29 to 25,
18 to 14
C9 to C0 I 10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to
Table 31 for input modes.
62 to 58,
55 to 51
S9 to S0 I 10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to
Table 31 for input modes.
30 CLKIN_A I Pixel Clock Input for HD only (74.25 MHz), ED
1
only (27 MHz or 54 MHz) or SD only (27 MHz).
63 CLKIN_B I
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
50
S_HSYNC
I/O
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
49
S_VSYNC
I/O
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and Vertical Synchronization Control section.
22
P_HSYNC
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
23
P_VSYNC
I
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
24
P_BLANK
I ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
48 SFL/MISO I/O
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
47 R
SET1
I
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
SET1
to
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
SET1
to AGND.
36 R
SET2
I
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
SET2
to AGND.
45, 35
COMP1,
COMP2
O Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
AA
.
Pin No. Mnemonic
Input/
Output Description
44, 43, 42
DAC 1, DAC 2,
DAC 3
O DAC Outputs. Full and low drive capable DACs.
39, 38, 37
DAC 4, DAC 5,
DAC 6
O DAC Outputs. Low drive only capable DACs.
21 SCL/MOSI I Multifunctional Pin: I
2
C Clock Input/SPI Data Input.
20 SDA/SCLK I/O Multifunctional Pin: I
2
C Data Input/Output. Also, SPI clock input.
19
ALSB/SPI_SS
I Multifunctional Pin: This signal sets up the LSB
2
of the MPU I
2
C address. Also, SPI slave select.
46 V
REF
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
41 V
AA
P Analog Power Supply (3.3 V).
10, 56 V
DD
P
Digital Power Supply (1.8 V). For dual-supply configurations, V
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1 V
DD_IO
P Input/Output Digital Power Supply (3.3 V).
34 PV
DD
P
PLL Power Supply (1.8 V). For dual-supply configurations, PV
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
33 EXT_LF1 I External Loop Filter for On-Chip PLL 1.
31 EXT_LF2 I External Loop Filter for On-Chip PLL 2.
32 PGND G PLL Ground Pin.
40 AGND G Analog Ground Pin.
11, 57 DGND G Digital Ground Pin.
64 GND_IO G Input/Output Supply Ground Pin.
1
ED = enhanced definition = 525p and 625p.
2
LSB = least significant bit. In the ADV7344, setting the LSB to 0 sets the I
2
C address to 0xD4. Setting it to 1 sets the I
2
C address to 0xD6.