Doc. No. MV-S105540-00, Rev. A
Document Classification: Proprietary Information Page 29
Signal Description
Pin Description
Table 12: Clock/Configuration/Reset/I/O
117-TFBGA
Pin #
96-aQFN
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
K2 B11 31 125CLK O Clock 125. A generic 125 MHz clock refer-
ence generated for use on the MAC device.
This output can be disabled via DIS_125
through the CONFIG[3] pin.
D8 A35 88 CONFIG[0] I CONFIG[0] pin configures PHY_ADR[2:0]
bits of the physical address.
Each LED pin is hardwired to a constant
value. The values associated to the CON-
FIG[0] pin are latched at the de-assertion of
hardware reset.
CONFIG[0] pin must be tied to one of the
pins based on the configuration options
selected. They should not be left floating.
For the Two-Wire Serial Interface (TWSI)
device address, the lower 5 bits, which are
PHYADR[4:0], are latched during hardware
reset, and the device address bits [6:5] are
fixed at ‘10’.
E9 B30 87 CONFIG[1] I CONFIG[1] pin configures PHY_ADR[4:3]
and ENA_PAUSE options.
Each LED pin is hardwired to a constant
value. The values associated to the CON-
FIG[1] pin are latched at the de-assertion of
hardware reset.
CONFIG[1] pin must be tied to one of the
pins based on the configuration options
selected. They should not be left floating.
For the TWSI device address, the lower 5
bits, which are PHYADR[4:0], are latched
during hardware reset, and the device
address bits [6:5] are fixed at ‘10’.
Copyright © 2020 Marvell
December 2, 2020
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