Microsemi ProASIC3/E

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UG0048 User Guide Revision 5.1 iv

8.1 I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Appendix: Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1 Top-Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 ProASIC3/E Starter Kit Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Main Page

Table of Contents3
Revision History7
Revision 5.17
Revision 5.07
Revision 4.07
Revision 3.07
Contents and System Requirements8
Kit Contents8
Table 1 Kit Contents8
Table 3 Table8
Hardware Components9
Proasic3/E Starter Kit Board9
Board Description and Usage10
Figure 1 Proasic3/E Starter Kit Board: Top-Level View10
PLL Parts and Usage on Proasic3/E11
Instructions for PLL Activation on Board11
Power Supply11
Figure 2 Power Supply Block Diagram11
Power Supply Connections of Daughter Card12
Power Supplies and Chaining Boards Together13
Programming the Proasic3/E Device with Flashpro14
Connecting the Flashpro4 Programmer to the Board14
Programming or Re-Programming the Design14
Jumpers for Isolating Switches and Leds from FPGA15
Clock Circuits16
40 Mhz Oscillator16
LED Device Connections17
Switches Device Connections17
LVDS Channels17
Table 5 Color Convention on CAT 5E Primary18
Table 6 Color Convention on CAT 5E Secondary18
Setup and Self Test20
Software Installation20
Hardware Installation20
Testing the Starter Kit Board20
Programming the Test File20
Description of Test Design21
Figure 3 Design Block Diagram21
Figure 5 Figure21
Figure 4 Data Block Diagram22
Table 8 Switches22
LVDS Signal Evaluation23
Hardware Test Setup23
Design Test Setup23
Figure 5 TX Portion of Test Design23
Measurement Results24
Figure 6 LVDS Signal Across RX Termination at 300 Mbps24
Testing the Board25
Equipment Required25
Equipment Provided to Testing Facility25
Testing Facility Equipment25
Test Procedure for the A3PE-STARTER-KIT-225
Initial Power-On Procedure25
Testing Board Functionality with A3PE1500-PQ208 Silicon26
Appendix: PQ208 Package Connections28
I/O Naming Conventions28
208-Pin PQFP29
Figure 7 208-Pin PQFP29
Table 9 Device Connections for 208-Pin PQFP30
Appendix: Board Schematics32
Top-Level View33
Figure 8 Top-Level View of Proasic3/E Starter Kit Board33
Figure 9 Bottom-Level View of Proasic3/E Starter Kit Board34
Proasic3/E Starter Kit Board Schematics35
Figure 10 Bottom-Level View of Proasic3/E Starter Kit Board35
Figure 11 Proasic3 FPGA36
Figure 12 Push-Button and Hex Switches37
Figure 13 FPGA Headers and Expansion Bus38
Figure 14 Clocks Oscillators and Reset39
Figure 15 Decoupling Caps, Test Points40
Figure 16 LVDS Signal Routing Via CAT-5E Connectors41

Microsemi ProASIC3/E - Page 4

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