7 Applied Instructions
7.3 Arithmetic and Logical Operation
180
FXCPU Structured Programming Manual
(Basic & Applied Instruction)
Extension function(FXU and FX2C PLCs)
The FXU PLC of V2.30 or earlier does not support the extension function.
When executing an instruction with M8023 ON, a binary float operation takes place.
In this case, K, H and D are valid as the object device for and and D is valid for .
The source data needs to be converted into binary float value in advance by FLT instruction.
Note, however, that constants K and H are automatically converted into binary float values.
Cautions
1) When handling 32-bit data in a structured program, a 16-bit device cannot be specified directly as in the
case of a simple project. Use a label to handle 32-bit data.
A 32-bit counter can be specified directly as it is a 32-bit long device.
Use a global label to specify a device.
2) The FX
0, FX0S or FX0N PLC does not support the instructions of pulse operation type.
To execute pulse operation, make the instruction execution condition pulse type.
3) When using a 32-bit operation instruction (DADD or DADDP) and specifying word devices, a 16-bit word
device on the low-order side is specified first, and a word device with the subsequent device number is
automatically set for the high-order 16 bits.
To prevent number overlap, it is recommended to always specify an even number, for example.
4) The same device number can be specified for both the source and the destination.
In this case, note that the addition result changes in every operation cycle if a continuous operation type
instruction (ADD or DADD) is used.
5) Some restrictions to applicable devices
S1:The FX
3U, FX3UC and FX3G PLCs only are applicable.
S2:The FX
3U and FX3UC PLCs only are applicable.
Program examples
1. Difference between ADD instruction and INC instruction caused by a program for adding
"+1".
When ADD[P] instruction is executed, "1" is added to the contents of D0 every time X001 turns ON from OFF.
ADD[P] instruction is similar to INCP instruction described later except the contents shown in the table below.
ADD/ADDP/DADD/DADDP INC/INCP/DINC/DINCP
Flag (zero, borrow, carry) Operates Does not operate
Operation result
16-bit
operation
+(+1)=
+32,767 → 0 → +1 → +2 → +32,767 → -32,768 → -32,767
+(-1)=
← -2 ← -1 ← 0 ← -32,768 -
32-bit
operation
+(+1)=
+2,147,483,647 → 0 → +1 → +2 → +2,147,483,647 → -2,147,483,648 → -2,147,483,647
+(-1)=
← -2 ← -1 ←0 ← -2,147,483,648 -
(D 0) + 25
→
(D 0)
X001
D0
D0
ADD
EN
s1
s2
ENO
d
K25
(D 0) +1 →( D 0)
X001
D0
D0
ADDP
EN
s1
s2
ENO
d
K1
INCP
EN ENO
d
X001
D0
[Structured ladder] [ ST ]
ADDP(X001, D0, K1, D0);
INCP(X001, D0);
(D 0) +1 →( D 0)
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