7 Applied Instructions
7.4 Rotation and Shift Operation
220
FXCPU Structured Programming Manual
(Basic & Applied Instruction)
Function and operation explanation
1. 16-bit operation (SFTR, SFTRP)
For "n1" bits (shift register length) starting from the bit device specified by , "n2" bits are shifted rightward
(1) and 2) shown below).
After shift, "n2" bits from the bit device specified by are transferred to "n2" bits from +n1-n2 (3)
shown below).
Cautions
1) Some restrictions to applicable devices
S1:Applicable only to the FX
3U and FX3UC PLCs. Not indexed (V, Z).
S2:The FX
3U, FX3UC and FX3G PLCs only are applicable.
2) The FX
0, FX0S or FX0N PLC does not support the instructions of pulse operation type.
To execute pulse operation, make the instruction execution condition pulse type.
3) Note that "n2" bits are shifted every time the command input turns ON from OFF in SFTRP instruction,
but that "n2" bits are shifted in each scan time (operation cycle) in SFTR instruction.
4) Limitation to n1 and n2 differs from one PLC to another.
Error
If the transfer source specified by is equivalent to the shifted device specified by , an operation error
occurs (error code: K6710). (Applicable only to the FX
3U and FX3UC PLCs)
PLC Limit
FX3U, FX3UC, FX3G, FX1N, FX2N, FX1NC, FX2NC, FX2,
FX
2C
n2≤n1≤1024
FX1S, FX0, FX0S, FX0N
n2≤n1≤512
SFTR
EN
s
n1
ENO
d
n2
Command input
Stored data
Shift data
Bit data length
Number of bits
"n2" bits are
shifted rightward
(n2 = 3).
Overflow
(data to be deleted)
Before
execution
After
execution
n2 (in the case of "n2 = 3")
n1 (in the case of "n1 = 9")
1)
3) Copy
2)
+1 +2
s ss
+8 +7 +6 +5 +4 +3 +2 +1
d d d d d d d d d
+2 to before shift (n2 = 3).
s s
+8 to +3 before shift (n2 = 3).
d d
+8 +7 +6 +5 +4 +3
d d d d d d
+2 +1
d d d
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