Mitsubishi Electric Q13UDVCPU - Page 555

553
APPENDICES
A
Appendix 3 List of Special Register Areas
SD781
to
SD785
Mask pattern
of IMASK
instruction
Mask pattern
The mask patterns masked by the IMASK instruction are
stored as follows.
S (During
execution)
New
Q00J/Q00/Q01
SD781
to
SD793
The mask patterns masked by the IMASK instruction are
stored as follows.
*1
*1: The Q00UJCPU, Q00UCPU, and Q01UCPU cannot
use SD786 to SD793.
Qn(H)
QnPH
QnPRH
QnU
LCPU
SD794
PID limit
setting (for
incomplete
derivative)
0: With limit
1: Without
limit
This register stores the limit of each PID loop as shown
below.
UNew
Q00J/Q00
/Q01
*1
SD794
to
SD795
This register stores the limit of each PID loop as shown
below.
Qn(H)
*4
QnPRH
QnU
LCPU
Number Name Meaning Explanation
Set by
(When
Set)
Corresponding
ACPU
D9
Corresponding
CPU
SD781
SD782
SD785
l63
l49
l48
l79
l127
l65
l113
l64
l112
b15 b0b1
to
to
to
to
to
SD781
SD782
SD793
l63
l49
l48
l79
l255
l65
l241
l64
l240
b15
b0b1
to
to
to
to
SD794
b15 b1 b0
b7b8
to
toto
Loop8 Loop2 Loop1
SD794
SD795
b15 b1 b0
to
to
to
Loop16
Loop32
Loop2
Loop18
Loop1
Loop17