Mitsubishi Electric Q13UDVCPU - Page 556

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*1 Modules whose function version B or later
*2 Modules whose serial number (first five digits) is "04012" or later
*3 Modules whose serial number (first five digits) is "07032" or later
*4 Modules whose serial number (first five digits) is "09012" or later
*5 Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU
*6 The range is 1 to 9 (default: 2) for the Q03UDCPU, Q04UDHCPU, and Q06UDHCPU whose serial number (first five
digits) is "10012" or earlier. If the number out of the range is set, the number 9 is set.
SD796
Maximum
number of
blocks used
for the
multiple CPU
high-speed
transmission
dedicated
instruction
(for CPU
No.1)
Range of the
maximum
number of
blocks:
1 to 7 (default: 2)
If the number out
of the range is
set, the number
7 is set.
*6
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.1). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.1, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM796 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
U (At 1
scan after
RUN)
New
QnU
*5
SD797
Maximum
number of
blocks used
for the
multiple CPU
high-speed
transmission
dedicated
instruction
(for CPU
No.2)
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.2). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.2, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM797 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
SD798
Maximum
number of
blocks used
for the
multiple CPU
high-speed
transmission
dedicated
instruction
(for CPU
No.3)
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.3). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.3, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM798 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
SD799
Maximum
number of
blocks used
for the
multiple CPU
high-speed
transmission
dedicated
instruction for
CPU No.4)
Specifies the maximum number of blocks used for the
multiple CPU high-speed transmission dedicated
instruction (target CPU=CPU No.4). When the multiple
CPU high-speed transmission dedicated instruction is
executed to the CPU No.4, and the number of empty
blocks of the dedicated instruction transmission area is
less than the setting value of this register, SM799 is
turned ON, which is used as the interlock signal for
consecutive execution of the multiple CPU high-speed
transmission dedicated instruction.
Number Name Meaning Explanation
Set by
(When
Set)
Corresponding
ACPU
D9
Corresponding
CPU