APP -6 APP -6
PPENDICES
MELSEC-Q
APPENDIX 1.2 Special Registers (SD)
Compatible CPU
No. Name Content Description
Setting Side
(Setting
Timing)
Basic model QCPU
High Performance
model QCPU
Process CPU
Redundant CPU
Universal model QCPU
SD90
SD91
SD92
SD93
SD94
SD95
SD96
SD97
SD98
SD99
Step transition
monitoring
timer setting
value
Timer set value
and F No. at
time-out
•
Set the set time of the step transition watch
dog timer and the annunciator No. (F No.)
that will turn ON at time-out of the watch
dog timer.
b15 b7 b0b8
F number setting
(0 to 255)
Timer time limit
setting
(1 to 255 sec:
(1-second units))
to to
• The timer starts when any of SM90 to
SM99 is turned ON during an active step,
and the set annunciator (F) turns ON if the
transition condition following the
corresponding step is not satisfied within
the timer time limit.
System
(at error
occurrence)
The special registers SD90 to SD99 correspond to the
following special relays.
Special register Special relay
SD90 SM90
SD91 SM91
SD92 SM92
SD93 SM93
SD94 SM94
SD95 SM95
SD96 SM96
SD97 SM97
SD98 SM98
SD99 SM99
To Next Page
Loading...
Need help?
General
