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4 SFC PROGRAM CONFIGURATION
MELSEC-Q
(2) Step END instruction (r)
(a) A specified step at a specified block is forcibly deactivated. “Coil HOLD” and “operation
HOLD” steps are subject to this instruction.
(b) When the number of active steps in the corresponding block reaches 0 due to the
execution of this instruction, END step processing is performed and the block becomes
inactive.
When the bock START/END bit of the SFC information devices has been set, the
corresponding bit device changes from ON to OFF.
(c) If the RST instruction is executed at a step located in a parallel branch, the parallel coupling
condition will remain unsatisfied.
(d) If a specified step is already inactive when this instruction is executed, the instruction will
be ignored (equivalent to the NOP instruction).
(e) When the operation output is used to end the step, do not specify the current step as the
specified step number.
If the current step is designated as the specified step number, normal operation will not be
performed.
S0
S2
S1
rS1
(f) Specify the step as described below.
1) In the case of SFC program
• Use "Sn" when specifying the step in the current block.
• Use "BLm\Sn" when specifying the step in another block.
2) In the case of sequence program
• Use "BLm\Sn" when executing the step END instruction in the sequence program.
• When the block number is not specified, specify the block number with the BRSET
instruction.
However, the BRSET instruction cannot be used for the Basic model QCPU and
Universal model QCPU.
Block 0" is set when the block number is not specified for the Basic model QCPU and
Universal model QCPU.
[Operation Error]
• When no specified step is present or the SFC program is in stand-by mode: Error No.4631
•
If using the own step as the specification step No. (Basic model QCPU and Universal
model QCPU only) :Error No.4505
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