The open architecture controller board uses Flash
memory (U715) in place of conventional EPROMs.
This allows the firmware to be reprogrammed
through the side connector without opening the
radio. The smart RIB box (SRIB) is used in con-
junction with the RSS software program to perform
the Flash reprogramming operation. While this
occurs, the SRIB applies 12.7 V at different times
to two of the radio side connector pins, 4 and 10.
Pin 4 is the OPT B+/BOOT SEL pin. When 12.7
volts is applied to this pin, zener diode VR713
starts conducting and turns on both transistors con-
tained in U703. The outputs of these transistors pull
the MODA/MODB pins of U705 low and also con-
trol mux logic involving U709 to separate the
microprocessor’s SCI TX and RX paths, which are
necessary for bootstrapping code into the µC dur-
ing Flash reprogramming. Diode CR701 is needed
to prevent current from flowing from the external
12.7 V source into the battery.
When 12.7 V is applied to pin 10 of the side con-
nector, current flows through diode CR705 and
approximately 12.0 V is presented to the Vpp pin of
Flash memory (U715), which is required for repro-
gramming. Resistor R723 and zener diode VR715
prevent excess voltage from appearing at the input
to U710-B6 when the 12.7 volts is applied.
3. Controller Board 5V Regulators
To reduce the possibility of digital noise coupling
into the audio circuitry, the controller board uses
separate analog and digital 5V supplies. The con-
troller board regulated 5V for the digital circuitry
(Vdd) is derived from a dedicated linear regulator
IC (U708) which also provides a low voltage reset
function. This device uses SW B+ as input and pro-
duces an output that is regulated to 5V ±0.1V. The
low voltage error output (U708 pin 5) is used to
hold the microprocessor (U705) RESET line low
during power turn-on and turn-off conditions or
when the battery is accidentally discharged to a
very low voltage; this prevents the microprocessor
from operating erratically during low voltage condi-
tions.
The regulated analog 5V supply (Vaud) from audio
PA U702 provides the operating voltage for audio
IC U701. It is generated in conjunction with the
external PNP pass transistor Q701. The circuit
uses a negative feedback loop with an internal dif-
ferential amplifier and a reference voltage inside
U702. As the load on the 5V changes, the amplified
error voltage is fed back to the base of transistor
Q701 to keep the 5V regulated to a tolerance of
±0.25V.
III. VHF/UHF TRANSCEIVER
A. Frequency Generation Unit (FGU)
The frequency generation unit (FGU) consists of
three major sections; the high stability reference oscilla-
tor (U203), the fractional-N synthesizer (U204,) and the
VCO buffer (U201). A 5V regulator (U202), supplies
power to the FGU. The synthesizer receives the 5V
REG at U204, and applies it to a filtering circuit within
the module and capacitor C253. The well filtered 5-volt
output at U204 pin 19 is distributed to the TX and RX
VCOs and the VCO buffer IC. The mixer LO injection
signal and transmit frequency are generated by the RX
VCO and TX VCO respectively. The RX VCO uses an
external active device (Q202), whereas the TX VCO
active device is a transistor inside the VCO buffer. The
base and emitter connections of this internal transistor
are pins 11 and 12 of U201.
The RX VCO is a Colpitts-type oscillator, with
capacitors C235 and C236 providing feedback. The RX
VCO transistor (Q202) is turned on when pin 38 of U204
switches from high to low. The RX VCO signal is
received by the VCO buffer at U201 pin 9, where it is
amplified by a buffer inside the IC. The amplified signal
at pin 2 is routed through a low-pass filter (L201 and
assocated capacitors) and injected as the first LO signal
into the mixer (U2 pin 8). In the VCO buffer, the RX
VCO signal (or the TX VCO signal during transmit) is
also routed to an internal prescaler buffer. The buffered
output at U201 pin 16 is applied to a low-pass filter
(L205 and associated capacitors). After filtering, the sig-
nal is routed to a prescaler divider in the synthesizer at
U204 pin 21.
The divide ratios for the prescaler circuits are deter-
mined from information stored in a codeplug, which is
part of the microprocessor (U705). The microprocessor
extracts data for the division ratio as determined by the
position of the channel-select switch (S401), and busses
the signal to a comparator in the synthesizer. A
16.8MHz reference oscillator, U203, applies the
16.8MHz signal to the synthesizer at U204 pin 14. The
oscillator signal is divided into one of three pre-deter-
mined frequencies. A time-based algorithm is used to
generate the fractional-N ratio.
If the two frequencies in the synthesizer’s compara-
tor differ, a control (error) voltage is produced. The
phase detector error voltage (V control) at pin 31 and 33
of U204, is applied to the loop filter consisting of resis-
tors R211, R212, and R213, and capacitors C244,
C246, C247 and C275 . The filtered voltage alters the
VCO frequency until the correct frequency is synthe-
sized. The phase detector gain is set by components
connected to U204 pins 28 and 29.
In the TX mode, U204 pin 38 goes high and U201
pin 14 goes low, which turns off transistor Q202 and
turns on the internal TX VCO transistor in U204. The TX
VCO feedback capacitors are C219 and C220. Varactor
12
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