MSA General Monitors S4100C - Register 7; Register 9; Register 10

Model S4100C
34
8.5.2 Register 7
Description
Bit position
Dec. value
Function
-
15-6
0
-
Analogue output at
calibration
5-4
0
1
2
0.0mA
1.5mA
2.0mA
A2 alarm open collector
output normally
energised/de-energised
3
0
1
De-energised
Energised
A1 alarm open collector
output normally
energised/de-energised
2
0
1
De-energised
Energised
A2 alarm open collector
output normally
latching/non-latching
1
0
1
Non-latching
Latching
A1 alarm open collector
output normally
latching/non-latching
0
0
1
Non-latching
Latching
8.5.3 Register 9
Description
Bit position
Dec. value
Node address
15-8
1-255
1 stop bit
2 stop bits
7
0
1
No parity
Odd parity
Even parity
6-5
0
1
2
-
4-2
0
Baud rate 19200
Baud rate 9600
Baud rate 4800
Baud rate 2400
1-0
0
1
2
3
The Node address specified in the high data byte is not written during a
broadcast write of the register.
8.5.4 Register 10
The clear register is written a value of 1 to clear a latched Fault or Alarm
indicated in the status register. Each issue of the clear command clears a
single latched Fault or Alarm in order of priority, provided the Fault or
Alarm condition no longer exists.