MSI G45TM-E53 Series - Page 59

BIOS Setup ▍
MS-7609
3-21
BIOS Setup ▍
MS-7609
DRAM Tmng Mode
Selects whether DRAM tmng s controlled by the SPD (Seral Presence Detect) EE-
PROM on the
DRAM module. Settng to [Auto By SPD] enables DRAM tmngs and
the followng related tems to be determned by BIOS based on the con󰘰guratons
on the SPD. Selectng [Manual] allows users to con󰘰gure the DRAM tmngs and the
followng related tems manually.
CAS Latency (CL)
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Ths controls
the CAS latency, whch determnes the tmng delay (n clock cycles) before SDRAM
starts a read command after recevng t.
tRCD
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. When DRAM
s refreshed, both rows and columns are addressed separately. Ths setup tem al-
lows you to
determne the tmng of the transton from RAS (row address strobe)
to CAS (column address strobe). The less the clock cycles, the faster the DRAM
performance.
tRP
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Ths settng
controls the number of cycles for Row Address Strobe (RAS) to be allowed to pre-
charge. If nsu󰘲c
ent tme s allowed for the RAS to accumulate ts charge before
DRAM refresh may be ncomplete and DRAM may fal to retan data. Ths tem ap-
ples only when synchronous DRAM s nstalled n the system.
tRAS
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Ths settng
determnes the tme RAS takes to read from and wrte to a memory cell.
tRTP
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Ths settng
controls the tme nterval between a read and a precharge command.
tRC
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. The row cycle
tme determnes the mnmum number of clock cycles a memory row takes to com-
plete a full cycle, from row actvat
on up to the prechargng of the actve row.
tWR
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. It spec󰘰es
the amount of delay (n clock cycles) that must elapse after the completon of a vald
wrte operaton, before an actve bank can be precharged. Ths delay s requred to
guarantee that data n the wrte bu󰘯ers can be wrtten to the memory cells before
precharge occurs.
tRRD
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Spec󰘰es the
actve-to-actve delay of d󰘯erent banks.
tWTR
When the DRAM Tmng Mode sets to [Manual], the 󰘰eld s adjustable. Ths tem
controls the Wrte Data In to Read Command Delay memory tmng. Ths consttutes
the mnmum number of clock cycles that must occur between the last vald wrte op-
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