AWARD
®
BIOS Setup
3-13
SDRAM RAS Precharge Time
This setting controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insufficient time is allowed for the RAS to accumu-
late its charge before DRAM refresh, refresh may be incomplete and DRAM
may fail to retain data. This item applies only when synchronous DRAM is
installed in the system. Setting options: 2, 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result. Setting options: Enabled, Disabled.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh,
resulting in better video performance. However, if any program writes to this
memory area, a system error may result. Setting options: Enabled, Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this
area is reserved, it cannot be cached. The user information of peripherals that
need to use this area of system memory usually discusses their memory
requirements. Setting options: Enabled, Disabled.
CPU Latency Timer
During Enabled, a deferrable CPU cycle will only be Deferred after it has been
in a Snoop Stall for 31 clocks and another ADS# has arrived. During Disabled,
A deferrable CPU cycle will be Deferred immediately after the GMCH receives
another ADS#.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles so that transactions to and from the ISA bus are buffered
and PCI bus can perform other transactions while the ISA transaction is
underway. Select Enabled to support compliance with PCI specification ver-
sion 2.1. Setting options: Enabled, Disabled.
On-Chip Video
The setting disables/enables the onchip video controller. Setting options:
Disabled, Enabled.
This Manual: http://www.manuallib.com/file/2541279
To Next Page
Loading...
