Chapter 3
3-12
Advanced Chipset Features
Note: Change these settings only if you are familiar with the chipset.
DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to Yes enables SDRAM Cycle Length
and DRAM Clock automatically to be determined by BIOS based on the con-
figurations on the SPD. Selecting No allows users to configure these fields
manually.
The Advanced Chipset Features setup options are used to change the values
of the chipset registers. These registers control most of the system options in
the computer.
CMOS Setup Utility - Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
Item Help
Menu Level 8
DRAM Timing by SPD Yes
SDRAM Cycle Length Auto
DRAM Clock Auto
Memory Hole Disabled
P2C/C2P Concurrency Enabled
Fast R-W Turn Around Enabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
Frame Buffer Size 8M
AGP Aperture Size 64M
OnChip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
OnChip Modem Auto
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Enabled
PCI#2 Access #1 Retry Enabled
x
x
↑ ↓ → ←:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
Memory Parity/ECC Check Disabled
To Next Page
Loading...
