National Instruments E Series - Appendix A; Daqcard-AI-16 E-4

Table of Contents
 National Instruments Corporation ix DAQCard E Series User Manual
Figures
Figure 1-1. The Relationship between the Programming Environment, NI-DAQ,
and Your Hardware ................................................................................1-4
Figure 2-1. A Typical Configuration for the DAQCard E Series Card ......................2-2
Figure 3-1. DAQCard-AI-16E-4 Block Diagram .......................................................3-1
Figure 3-2. DAQCard-AI-16XE-50 Block Diagram ..................................................3-2
Figure 3-3. Dither .......................................................................................................3-7
Figure 3-4. Analog Trigger Block Diagram ...............................................................3-9
Figure 3-5. Below-Low-Level Analog Triggering Mode ...........................................3-10
Figure 3-6. Above-High-Level Analog Triggering Mode ..........................................3-10
Figure 3-7. Inside-Region Analog Triggering Mode ..................................................3-11
Figure 3-8. High-Hysteresis Analog Triggering Mode ..............................................3-11
Figure 3-9. Low-Hysteresis Analog Triggering Mode ...............................................3-12
Figure 3-10. CONVERT* Signal Routing ....................................................................3-13
Figure 4-1. I/O Connector Pin Assignment for the DAQCard-AI-16E-4 and
DAQCard-AI-16XE-50 ..........................................................................4-2
Figure 4-2. DAQCard E Series PGIA .........................................................................4-11
Figure 4-3. Summary of Analog Input Connections ..................................................4-13
Figure 4-4. Differential Input Connections for Ground-Referenced Signals .............4-15
Figure 4-5. Differential Input Connections for Nonreferenced Signals .....................4-16
Figure 4-6. Single-Ended Input Connections for Nonreferenced or Floating Signals 4-19
Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signals ..........4-20
Figure 4-8. Digital I/O Connections ...........................................................................4-21
Figure 4-9. Timing I/O Connections ..........................................................................4-23
Figure 4-10. Typical Posttriggered Acquisition ...........................................................4-25
Figure 4-11. Typical Pretriggered Acquisition .............................................................4-25
Figure 4-12. SCANCLK Signal Timing .......................................................................4-26
Figure 4-13. EXTSTROBE* Signal Timing ................................................................4-27
Figure 4-14. TRIG1 Input Signal Timing .....................................................................4-28
Figure 4-15. TRIG1 Output Signal Timing ..................................................................4-28
Figure 4-16. TRIG2 Input Signal Timing .....................................................................4-30
Figure 4-17. TRIG2 Output Signal Timing ..................................................................4-30
Figure 4-18. STARTSCAN Input Signal Timing .........................................................4-31
Figure 4-19. STARTSCAN Output Signal Timing ......................................................4-32
Figure 4-20. CONVERT* Input Signal Timing ...........................................................4-33
Figure 4-21. CONVERT* Output Signal Timing .........................................................4-34
Figure 4-22. SISOURCE Signal Timing ......................................................................4-35
Figure 4-23. UISOURCE Signal Timing ......................................................................4-36
Figure 4-24. GPCTR0_SOURCE Signal Timing .........................................................4-37
Figure 4-25. GPCTR0_GATE Signal Timing in Edge-Detection Mode .....................4-38