Functions
Outline
The
hlSlI80C85A uses a multiplexed data and address bus.
The upper eight bits of an
address are output to
the address bus and the lower eiglit bits to the addresstdata
bus.
The
lower eight-bit addresses can be output only in the first state in each machine
cycle. They must be held in an external latch by simultaneously using ALE. The
addrestdata bus serves as a bilateral data bus the same way as in the hfSh18080A.
Data is ti-ansferred on the bilateral data bus. The CPU outputs
RD.
WR,
and
IO/~
signals for bus control signal and INTA for interrupt reception. The CPU receives
HOLD: READY. and interrupt signals
synchronized with the clock.
For serial transmission
of data, serial-data input SID and serial-data
output SOD. are
available. Three
maskable restart interrupts
and
onc i~nmaskable TRAP interrup~ are
available in addition to those of
the hiSM8080A.
Status data
Status data is a signal
lliat indicates the bus cyclc status.
This signal is output frorn
pins SO or S1 and held until completion of the cycle.
In contrast to the
.CISX180C85A.
status data in the hlShI8080A are output from data bus at the start of each machine
cycle.
Bus status are given as follows:
HALT 0 0
READ
1
0
FETCH
1
1
Interrupts and serial
110
The EvISkf80C85A is provided with five interrupt input lines: INTR: RST5.5. RST6.5,
RST7.5, and TRAP.
INTR functions the same as the
lISM8080A INT. RST input
lines
5.5. 6.5, and 7.5 are all niaskable restart interrupts. TRAP is an unmaskable
restart interrupt. Restart
interrupt priority is determined in terms of the restart
address, how to sense interrupt, and internal priority. TRAP has highest priority.
followed by RST7.5. RST6.5. RST5.5 and INTR.
h'ote that this preferential order is not taken into accouiit for routines already running
even if higher-preference interruption is made to them.
If RST5.5 is asserted during
an
RST7.5 routine, execution of RST7.5 is suspended.
RST6.5. RST5.5. and INT should
all be asserted until their interrupt requests are acknowledged.
While RST7.5 may be
input in the
for111 of pulse because its request is detected at its leading edge to be
set.
.A
request thus set is held until it is satisfied or SIlI or RESET instructions release
the request state.
An
RST7.5 request can be set even if masked: interruption is
inhibited.
TRAP is detected at its
leacling edge and should be asserted until the request is
accepted.
Before TRAP can be accepted a second time.
it
must first be disasserted.
To Next Page
