Omron SYSMAC CP2E-N D Series User Manual

9
CP2E CPU Unit Software User’s Manual(W614)
4-3 Function Blocks....................................................................................................................... 4-8
4-3-1 Overview of Function Blocks.......................................................................................................4-8
4-3-2 Advantages of Function Blocks................................................................................................... 4-8
4-3-3 Function Block Specifications ...................................................................................................4-10
4-3-4 ST Language.............................................................................................................................4-12
4-4 Programming Instructions.................................................................................................... 4-14
4-4-1 Basic Understanding of Instructions ......................................................................................... 4-14
4-4-2 Operands ..................................................................................................................................4-15
4-4-3 Instruction Variations................................................................................................................. 4-16
4-4-4 Execution Conditions ................................................................................................................ 4-16
4-4-5 Specifying Data in Operands .................................................................................................... 4-18
4-4-6 Data Formats ............................................................................................................................4-20
4-4-7 I/O Refresh Timing....................................................................................................................4-22
4-5 Constants ............................................................................................................................... 4-23
4-6 Index Registers ...................................................................................................................... 4-26
4-6-1 What are Index Registers?........................................................................................................4-26
4-6-2 Using Index Registers ...............................................................................................................4-26
4-6-3 Monitoring Index Registers ....................................................................................................... 4-30
4-7 Specifying Offsets for Addresses ........................................................................................ 4-32
4-7-1 Overview ................................................................................................................................... 4-32
4-7-2 Application Examples for Address Offsets ................................................................................ 4-34
4-8 Ladder Programming Precautions...................................................................................... 4-35
4-8-1 Special Program Sections.........................................................................................................4-35
Section 5 I/O Memory
5-1 Overview of I/O Memory Areas............................................................................................... 5-2
5-1-1 I/O Memory Areas....................................................................................................................... 5-2
5-1-2 I/O Memory Area Address Notation ............................................................................................ 5-5
5-1-3 I/O Memory Areas....................................................................................................................... 5-6
5-2 I/O Bits ...................................................................................................................................... 5-7
5-3 Work Area (W) .......................................................................................................................... 5-8
5-4 Holding Area (H) ...................................................................................................................... 5-9
5-5 Data Memory Area (D) ........................................................................................................... 5-11
5-6 Timer Area (T) ........................................................................................................................ 5-13
5-7 Counter Area (C) .................................................................................................................... 5-15
5-8 Index Registers (IR) ............................................................................................................... 5-17
5-9 Data Registers (DR) ............................................................................................................... 5-21
5-10 Auxiliary Area (A)................................................................................................................... 5-23
5-11 Condition Flags...................................................................................................................... 5-25
5-12 Clock Pulses .......................................................................................................................... 5-27
Section 6 I/O Allocation
6-1 Allocation of Input Bits and Output Bits ............................................................................... 6-2
6-1-1 I/O Allocation............................................................................................................................... 6-2
6-1-2 I/O Allocation Concepts............................................................................................................... 6-3
6-1-3 Allocations on the CPU Unit........................................................................................................ 6-3
6-1-4 Allocations to Expansion Units and Expansion I/O Units ............................................................ 6-4
Section 7 PLC Setup
7-1 Overview of the PLC Setup..................................................................................................... 7-2
7-2 PLC Setup Settings ................................................................................................................. 7-3
7-2-1 Startup and CPU Unit Settings ................................................................................................... 7-3
7-2-2 Timing and Interrupt Settings...................................................................................................... 7-4

Omron SYSMAC CP2E-N D Series Specifications

General

Brand	Omron
Model	SYSMAC CP2E-N D Series
Category	Computer Hardware
Language	English