TX-SR604/604E/8460
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -4
TERMINAL DESCRIPTION (1/2)
Pin Mnemonic Input/Output Function
1 VS/VACTIVE O VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
2 HS/HACTIVE O
3, 14 DVSSIO G Digital I/O Ground
4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V)
5-8, 19-24, P15-P0 O Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15-P8),
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
32, 33, 73-76
9, 31, 71 DVSS1-3 G Ground for Digital Supply
10, 30, 72 DVDD1-3 P Digital Supply Voltage (3.3 V)
11 AFF O Almost Full Flag. A FIFO control signal indicating when the FIFO has
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
12 HFF/QCLK/GL I/O Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
13 AEF O Almost Empty Flag. A FIFO control signal, it indicates when the FIFO
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
16 CLKIN I Asynchronous FIFO Clock. This asynchronous clock is used to output
data onto the P19-P0 bus and other control signals.
17, 18, 34, 35 GPO[3:0] O General-Purpose Outputs controlled via I C
25 LLCREF O Clock Reference Output. This is a clock qualifier distributed by the inter-
nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled
by the PLLCREF bit.
26 LLC2 O Line-Locked Clock System Output Clock/2 (13.5 MHz)
27 LLC1/PCLK O Line-Locked Clock System Output Clock. A dual-function pin (27 MHz 5%)
or a FIFO output clock ranging from 20 MHz to 35 MHz.
28 XTAL1 O Second terminal for crystal oscillator; not connected if external clock
source is used.
29 XTAL I Input terminal for 27MHz crystal oscillator or connection for external
oscillator with CMOS-compatible square wave clock signal
36 PWRDN I Power-Down Enable. A logical low will place part in a power-down status.
37 ELPF I This pin is used for the External Loop Filter that is required for the LLC PLL.
38
PVDD
P
39
PVSS G
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
2
Q4001: ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
To Next Page
Loading...
Need help?
General
