Panasonic DMR-BWT955GL - Analog Timer Block Diagram

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11.3. Analog Timer Block Diagram
JC_P_ON_DL_H
IC59501
(TIMER)
IC59505
(RESET)
IC59502
(RESET)
1
OUT
4
OPEN/
CLOSE
S7202
IR7201
REMOTE CONTROL
RECEIVER
OUT
IC58401
(RESET)
HDD_PFAIL_L
1
OUT
31
14
PFAIL[L]
LCD_TXD
LCD_CLK
RESET
1
27
KEYIN3
KEYIN1
REMOCON
P7406 P58813
8
DIGITAL P.C.B.
FRONT P.C.B.
P7201
9
P7407
P7406
P58813
P7201
128
P7407
P58813
P7201
10
P7407
P7406
P7406
P58813
1
32
9
X59501
10MHz_IN
10MHz_OUT
32.768KHz_OUT
32.768KHz_IN
28
HDMI_MONI(CEC_IN)
26
HDMI_CEC_OUT
10MHz
X59502
32.768KHz
Q59503
Q59507
Q59506,
SWITCHING
BUFFER
JK55001-13PIN
P58813
11
P7406 P7407 P7201
P58813
2
3
2
P7406 P7407 P7201
3
P7407 P7201
18
20
42
22
29
23
17
30
49
JC_P_ON[H]
JC_P_ON_H
55
HDMI_P_ON[H]
HDMI_P_ON_H
56
JC_P_ON_DL_H
XMPREQ
G_SCLK_A
G_XINTP_A
G_XINTM_A
QR59506
QR59505
PW_X_SW3.3V
IC51001
(HD DEC/ENC/CPU/GFX Process/
DDR3-IF/RTSC/AV Core/Graphics)
VDD
GND
IR
PW_XN_3.3V
PW_XN_3.3V
PW_X_SW12.0V
MAIN P.C.B.
Q59508
P58813
P7406
TO DIGITAL P.C.B.
REGULATOR BLOCK
DIAGRAM
P_STANDBY_H
JC_P_ON_H
HDMI_P_ON_H
JC_P_ON_DL_H
P_STANDBY_H
XINTM_OUT
XINTP_OUT
TBUS_CLK
XINTM[TBUS]
XMPREQ[TBUS]
UARTP2M/TBUS_TXD
UARTM2P/TBUS_RXD
XRES_PKS
PEAKS_STATE
AK4
AL3
AP2
XINTM
TXCLK
SCLKM
AP4
XRST
AP4
XSRST
SD_BOOT
AL4
SDBOOT
Q59501,Q59502
P58810
1
P58810
3
FAN MOTOR
M
Timer Block Diagram
15
G_SBPTM_A
16
G_SBMTP_A
51
57
63
AJ4
XMPREQ
AP3
AN4
SBPTM
SBMTP
62
47
FANLOCK
FAN_DA
LCD_CS
32
59
HDD_PFAIL[L]
43
DR_P_ON[H]
DR_P_ON_H
DR_P_ON_H
IC7201
DP7201
(DISPLAY DRIVE)
3
DIO
2
CLK
1
5
CSB
VDD
41 LED1
42 LED0
REC1
D7201
D7202
REC2
XN3.3V
LCD_5V
SEG0
SEG4
11
15
COM0
COM3
7
10
COM3
COM0
1
4
SEG5
SEG25
36
SEG25
SEG0
5
30
16
VLCD
DMR-BWT955GL
S7201
POWER
7
14
6
39
D7203
REC3
LED3
FRONT P.C.B.
MAIN P.C.B.
P7201
6
P7407
3
8
12
11