Panasonic DMR-EZ49VEG

S-77
ABBREVIATIONS
INITIAL/LOGO
PLLOK PLL LOCK
PWMCTL PWM OUTPUT CONTROL
PWMDA PULSE WAVE MOTOR DRIVE A
PWMOA, B PULSE WAVE MOTOR OUT A, B
R RE READ ENABLE
RFENV RF ENVELOPE
RFO RF PHASE DIFFERENCE OUTPUT
RS (CD-ROM) REGISTER SELECT
RSEL RF POLARITY SELECT
RST RESET
RSV RESERVE
S SBI0, 1 SERIAL DATA INPUT
SBO0 SERIAL DATA OUTPUT
SBT0, 1 SERIAL CLOCK
SCK SERIAL DATA CLOCK
SCKR AUDIO SERIAL CLOCK RECEIVER
SCL SERIAL CLOCK
SCLK SERIAL CLOCK
SDA SERIAL DATA
SEG0~UP FL SEGMENT OUTPUT
SELCLK SELECT CLOCK
SEN SERIAL PORT ENABLE
SIN1, 2 SERIAL DATA IN
SOUT1, 2 SERIAL DATA OUT
SPDI SERIAL PORT DATA INPUT
SPDO SERIAL PORT DATA OUTPUT
SPEN SERIAL PORT R/W ENABLE
SPRCLK SERIAL PORT READ CLOCK
SPWCLK SERIAL PORT WRITE CLOCK
SQCK SUB CODE Q CLOCK
SQCX SUB CODE Q DATA READ CLOCK
SRDATA SERIAL DATA
SRMADR SRAM ADDRESS BUS
SRMDT0~7 SRAM DATA BUS 0~7
SS START/STOP
STAT STATUS
STCLK STREAM DATA CLOCK
STD0~UP STREAM DATA
STENABLE STREAM DATA INPUT ENABLE
STH SOURCE START PULSE
STSEL STREAM DATA POLARITY SELECT
STV GATE DRIVER SCAN START PULSE
STVALID STREAM DATA VALIDITY
SUBC SUB CODE SERIAL
SBCK SUB CODE CLOCK
SUBQ SUB CODE Q DATA
SYSCLK SYSTEM CLOCK
T TE TRACKING ERROR
TIBAL BALANCE CONTROL
TID BALANCE OUTPUT 1
TIN BALANCE INPUT
TIP BALANCE INPUT
TIS BALANCE OUTPUT 2