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Panasonic KX-NS0154 - Page 42

Panasonic KX-NS0154
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42
KX-NS0154
P14 VREF Reference Voltage Powered by VCCA for Filtering PO
P15 MICPWR0 Microphone Power 0 Output PO
P16 SINGIN1 Input of Single-ended In Amplifier 1 (Not used) I
P17 DCIN2 DC A/D Input 2 (Not used) I
P18 TPS Not used I/O
P19 XO13M 13.824 MHz XTAL out (NC in external oscillator mode) O
R1 MIIRXCK_RGMIIRXC RX Clock I
R2 MIICRS_DV_RGMIIRX_CTL MII Carrier Sense I
R3 MIIRXD0_RGMIIRD0 MII RX Data I
R4 MDIO Management Data I/O Line I/O
R5 NFLREADY1_MEMXA22 NFL Ready I
R6 NFLD7_MEMXA21 NFL Data I/O
R7 EXTINT3_CLK_REF_OUT STRAP pin I
R8 EXTINT1_IIC1SCL I2C clock O
R9 KEY_ROW3 DIP SW detect I
R10 KEY_COL5 Trace (Not used) O
R11 U1RX UART1 Serial Data Input I
R12 U1RTS_DIGMIC_CLK UART1 Ready To Send (Not used) O
R13 FORCEMUTE Hardware Force Mute Function I
R14 LEDSINK2 LED Sink 2 (Not used) O
R15 VDD12_DCLS Class D Digital 1.2 V (Input)1 PI
R16 VSS Digital GND of Analog Blocks P
R17 VSS Digital GND of Analog Blocks P
R18 TPY1 Not used I/O
R19 DCIN0 DC A/D Input 0 (Not used) I
T1 MIITXEN_RGMIITX_CTL MII TX Enable O
T2 MIIREFCK_RGMIITXC MIITXCK I
T3 MIICOL_U2RX MII Collision O
T4 NFLRD_MEMXA24 NFL Read O
T5 NFLCS0_MEMXA18 NFL Chip Select O
T6 NFLD4_QDQ3 NFL Data I/O
T7 NFLD5_QCS0 NFL Data I/O
T8 KEY_ROW0 DIP SW detect I
T9 KEY_COL1 DIP SW detect I
T10 KEY_COL4 Trace (Not used) O
T11 U1TX UART1 Serial Data Output O
T12 TEST_ANA Analog Test Select (Not used) I
T13 EXT_REG_CTL Output Enable for External Regulator (Not used) O
T14 DCDC_VSENS Core DCDC Voltage Sense (Not used) I
T15 SINK_DCLS Class D Power Amplifier Ground P
T16 SINK_DCLS Class D Power Amplifier Ground P
T17 TPX1 Not used I/O
T18 TPY2 Not used I/O
T19 GNDI GND1 Connection P
U1 MIITXD1_RGMIITD1 MII TX Data O
U2 MIITXD0_RGMIITD0 MII TX Data O
U3 USB1N USB1 Negative I/O
U4 NFLALE_MEMXA17 NFL Address Latch O
U5 NFLWR_MEMXA23 NFL Write O
U6 NFLD1_QDQ0 NFL Data I/O
U7 EXTINT0_IIC1SDA I2C data I/O
U8 KEY_ROW1 DIP SW detect I
U9 KEY_COL0 DIP SW detect I
U10 KEY_ROW6_IIC2SCL Trace (Not used) O
U11 EXTINT8_DRV_Vbus Not used I
U12 DCINS DC Power Supply Sense (Not used) I
U13 PWM0 PWM Output 0 (Not used) O
U14 VCC5V_DCDC 5V Supply Voltage Input to the Core DCDC Regulator PI
U15 VDD18_DCLS Class D Digital 1.8 V (Input) PI
U16 VCC5V_DCLS Class D Supply Voltage (Output Amplifiers) PI
U17 VCC5V_DCLS Class D Supply Voltage (Output Amplifiers) PI
U18 VSS Digital GND of Analog Blocks P
U19 DCIN1 DC A/D Input 1 (Not used) I
V1 MIITXD3_RGMIITD3 MII TX Data O
V2 MIITXD2_RGMIITD2 MII TX Data O
V3 USB1P USB1 Positive I/O
V4 NFLD3_QDQ2 NFL Data I/O
Pin No. Terminal Name Contents of Control I/O setting Remark

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