9-5-7 FPGAb_CONFIG
R3846
NC/1K 1/16W
FB3804
120R
1 2
R3849 NC/0R05 OHM
K7-TMS
R3850 NC/0R05 OHM
CN1192
1
2
3
4
5
6
78
L
a
y
o
u
t
:
Near FPGA pins
FPGA-RESET
FPGA-RESET 6
L
a
y
o
u
t
:
Place near FPGA
If possible, place on TOP layer
GND-trace + GND-vias around the circuit
TP4069
+VCCO14
X3801
NC/148.5MHz
OE
1
NC
2
GND
3
OUT
4
OUT
5
VDD
6
L
a
y
o
u
t
:
Place close to X3801
C3808
NC/100N16V
L
a
y
o
u
t
:
100Ohm diff + TOP layer
Keep traces short
+3V3
FB3802
NC/ 120R
1 2
SSC-SEL0
U3700-27
XC 7K160T-2FBG676I4397
GNDADC_0_M11
M11
K7-PUDC-B
PQ-CLK-SYS 9
PQ-CLK-SYS
C3804 220nF 16V
C0-DDR-SYS-CLKn
C0-DDR-SYS-CLKp
PQ-CLK-SYS-SSSSC-SEL1
SW3801
1 2
3 4
K7-TCK
K7-PUDC-B 9
L
a
y
o
u
t
(
X
i
l
i
n
x
r
e
c
o
m
m
e
n
d
a
t
i
o
n
)
:
Route as 50 Ohm single ended
Avoid vias where possible
K7-CCLK 6
K7-CCLK
R3847 NC/4. 7K 1/16W
C0-DDR-SYS-CLKn 10
C0-DDR-SYS-CLKn
E
M
E
R
A
L
D
DDR REF CLOCK C0 148.5 / 200M Hz
K7-PUDC-B
Q4301
MMBT3904
L
a
y
o
u
t
:
Place near FPGA
If possible, place on TOP layer
GND-trace + GND-vias around the circuit
L
a
y
o
u
t
:
a
d
d
t
x
t
F
P
G
A
J
T
A
G
TP3809
SDA-BE
SCL-BE
R3851 47R 5%
D
B
G
S
W
3
8
0
1
E
M
E
R
A
L
D
RECONFIGURATION
PQ-VB1-TX0p 9,12
PQ-VB1-TX0n 9,12
SDA-BE 6,11,12
SCL-BE 6,11,12
R3843 NC/4. 7K 1/16W
E
M
E
R
A
L
D
CONFIG DONE
PQ-VB1-TX1p 9,12
PQ-VB1-TX1n 9,12
PQ-VB1-TX2p 9,12
PQ-VB1-TX2n 9,12
PQ-LED0 9
U3804
CDC S502PWR
XIN
1
SSC_SEL0
2
SSC_SEL1
3
GND
4
FS
5
OUT
6
VDD
7
XOUT
8
PQ-VB1-TX3n 9,12
PQ-RX-LOCKn 6,9
PQ-VB1-TX4p 9,12
PQ-VB1-TX4n 9,12
PQ-VB1-TX3p 9,12
PQ-VB1-TX2n
PQ-VB1-TX6n 9,12
PQ-VB1-TX5p 9,12
PQ-VB1-TX5n 9,12
PQ-VB1-TX3p
PQ-VB1-TX7n 9,12
PQ-VB1-TX6p 9,12
PQ-VB1-TX4n
PQ-VB1-TX4p
PQ-VB1-TX5p
PQ-VB1-TX6p
PQ-VB1-TX7p
PQ-VB1-TX3n
PQ-VB1-TX7n
PQ-VB1-TX1p
PQ-VB1-TX0n
PQ-VB1-TX2p
PQ-VB1-TX5n
PQ-VB1-TX6n
PQ-VB1-TX0p
PQ-VB1-TX1n
PQ-RX-LOCKn
PQ-VB1-TX7p 9,12
PQ-HTPDn 9,12
PQ-LOCKn 9,12
K7-ADC-Vn
PQ-HTPDn
PQ-LOCKn
+VCCADC
K7-ADC-Vp
C3807
33P 50V
R3807 0.05R
R3811 0.05R
R3812 0.05R
TP3815
TP3813
R3833
10 OHM
R3806 4.7K
R3816 10 OHM
PQ-LED1 9
K7-FCS-B 6,9
R3838
10K 5%
+3V3
R3841
NC/ 22K 1/16W
PQ-LOCKn
R3831 1M
K7-PROG-B
PQ-LED3 9
PQ-LED2 9
+3V3
C3801 NC /1uF 10V
BE-RESETn 6,11,12
BE-RESETn
R3802 10 OHM
K7-CCLK
TP3826
S
O
8
WIDE
R3835 NC/10OHM1/16W
PQ-RESET-SYSn 9
K7-D03
TP3805
R3803 0.05RR3819 NC/1K 1/16W
TP3804
+VCCADC
R3814 10 OHM
C3800
100NF 16V
K7-CCLK
K7-D00
K7-CCLK
K7-D01
K7-FCS-B
C
N
1
0
4
8
E
M
E
R
A
L
D
SPI FLASH DIRECT PROGRAM M ING
K7-D01
TP3803
K7-D00
K7-FCS-B
+3V3
GND-ADC
TP3802
CN1048
1
2
3
4
5
6
78
TP3816
D
B
G
TP3817
R3800 330R 5%
R3837
10K 5%
R3817 0.05R
D
B
G
GND-ADC
R3826 47 OHM
+3V3
K7-TCK
K7-TDI
K7-TMS K7-D02
K7-TDO
R3809 4.7K
K7-DONE
R3808 4.7K
R3804 0.05R
R3805 0.05R
R3810 4.7K
R3840
NC/22K 1/16W
PQ-CLK-SYS
J
T
A
G
P
R
O
G
R
A
M
M
I
N
G
C
N
1
0
9
4
E
M
E
R
A
L
D
L
a
y
o
u
t
:
A
d
d
t
x
t
2
5
M
H
z
TP3822
L
a
y
o
u
t
:
A
d
d
p
c
b
-
t
x
t
F
P
G
A
S
P
I
F
L
A
S
H
TP3820
R3815 10 OHM
PQ-CLK-SYS-SS
L
a
y
o
u
t
:
A
d
d
p
c
b
t
x
t
P
R
O
G
-
B
PQ-CLK-SYS-SS 10
C0-DDR-SYS-CLKp 10
C0-DDR-SYS-CLKp
TP3821
FB3801
120R
1 2
TP3823
TP3825
R3832
1K
+VCCO0
R3801 4.7K
R3834 22K
K7-PROG-B
FPGA-RESET
C3803 0.22UF
K7-D00 6,9
1
m
m
(
6
p
i
n
)
+VCCO0
K7-D01 6,9
C3805 100NF 16V
K7-D02 9
R3813 10 OHM
TP3818
K7-D03 9
GND-ADC
U3803
74LVC2G04GW
1A
1
GND
2
2A
3
2Y
4
VCC
5
1Y
6
TP3806
TP3819
K7-PROG-B
X3800
25MHz
1
24
3
+VCCO0
F
P
G
A
E
M
E
R
A
L
D
C
O
N
F
I
G
U
R
A
T
I
O
N
K7-TDO
R3821 100K
R3818 0.05R
C3806
33P 50V
GND-ADC
TP3807
E
M
E
R
A
L
D
SYSTEM CLOCK 25M Hz
TP3810
TP3814
TP3811
R3820 100K
TP3812
PQ-RESET-SYSn
PQ-HTPDn
TP3808
K7-TDI
K7-D01
K7-D03
PQ-RESET-SYSn
PQ-LED1
PQ-LED2
PQ-LED3
K7-D02
K7-FCS-B
K7-D00
BE-RESETn
PQ-LED0
TP3801
C3810
6.8PF 50V
C3811
6.8PF 50V
X3802
25MHz
1
24
3
E
M
E
R
A
L
D
SYSTEM CLOCK 25M Hz SS
K7-D03
w
e
a
k
p
u
l
l
u
p
r
e
c
o
m
m
e
n
d
e
d
b
y
X
i
l
i
n
x
o
n
T
C
K
/
T
M
S
weak pullup recommended by B&O on TDO (higher JTAG speed)
-> provision added into layout
(default NC; as no need seen on Quabber)
U3700-1
XC 7K160T-2FBG676I4397
VN_0
P11
VP_0
N12
CCLK_0
C8
CFGBVS_0
P7
DONE_0
J7
DXN_0
R11
DXP_0
R12
IN IT_B_0
G7
M0_0
T5
M1_0
T2
M2_0
P5
PROGRAM_B_0
P6
TCK_0
L8
TDI_0
R6
TDO_0
R7
TMS_0
N8
VCCADC_0
M12
VCCBATT_0
E8
VREFN _0
N11
VREFP_0
P12
SSC-SEL1 10
SSC-SEL0 10
SSC-SEL1
R3845
0.05R
SSC-SEL0
L
a
y
o
u
t
:
Place U3801 & U3802 next to eachother
Place U3801 & U3802 not to far from FPGA
Place CN1048 near U3801 & U3802 (as close a possible with heatsink restrictions)
R3848 N C/0R05 OHM
U3801
MX25L12833FM
CS#
1
SO/SIO1
2
WP#/SIO2
3
GND
4
SI/SIO0
5
SCLK
6
RESET#/SIO3
7
VCC
8
LED3800
GPTS06033GC1-PB
12
D
B
G
LED3801
GPTS06033GC1-PB
12
LED3802
GPTS06033GC1-PB
12
D
B
G
LED3803
GPTS06033GC1-PB
12
L
a
y
o
u
t
:
LEDs on TOP layer
LEDs next to each other (in logic order)
Add pcb txt LED0, LED1, LED2 and LED3
R3836
470R
+3V3
R
1
R
2
Q3800
LMUN5211T1G
1
32
K7-DONE
L
a
y
o
u
t
:
All LEDs on TOP layer (but not underneath heatsink)
Add pcb txt CONFIG DONE
D
B
G
D
B
G
+3V3
R3828
470R
R3827
470R
R3830
470R
R3829
470R
D
B
G
DBG
+3V3
DBG
DBG
+3V3
DBG
DBG
+3V3
PQ-LED0
PQ-LED1
PQ-LED2
PQ-LED3
R3842
22K
LED3804
GPTS06033GC1-PB
12
DBG
DBG
+1V8-FPGA
C3809
100NF 16V
FB3800
120R
1 2
Layout:
Place this complete circuit on the
same position as original circuit.
TP4068
Layout:
Place close to U3804
Layout:
- Route PQ-CLK-SYS inbetween SSC-SEL0 and SSC-SEL1
- Use the same path as the original differential signal for the 3 signals (BOTTOM layer)
+3V3
FB3803
120R
1 2
R3844 NC/4. 7K 1/16W
To Next Page
Loading...
