Philips S37SD-YD02 - Page 43

Block Diagrams, Test Point Overview, and Waveforms
EN 43SDI PDP 6.
Figure 6-7 Block diagram (50" HD v3)
Figure 6-8 Block diagram (50" HD v4)
- Vcc : Voltage for Logic Control
- Vdd : Voltage for FET driver
- Va : Voltage for address pulse
- Vsc_l
: Voltage sustain low
- Vscan : Voltage for scan high
- Vb : Voltage for X bias
- Vset : Voltage for Y ramp pulse
Reference
1366× 768 Pixels
1366× 3× 768 Cells
YPulse
Generator
Row
Driver
Vsync
Enable
Hsync
DCLK
DRAM
Display
Data
Driver
Timing Controller
Driver
Timing
Scan
Timing
VsVaVcc Vdd
DATA_R
8(9)Bi ts
Column Driver
LOGIC CONTROL
DRIVER CIRCUIT & PANEL
DATA_G
8(9)Bi ts
DATA_B
8(9)Bi ts
Input Data Processor
Data Con troller
XPulse
Generator
Vset
Vscan
Vb
LVDS
Interface
Column Driver
Vsc_l
F_14991_019.eps
030805