Philips TE3.1E CA - Page 35

Circuit Description and Abbreviation List
EN 35TE3.1E CA 9.
9.4.2 ST92195C/D
Figure 9-2 Internal block diagram and pin configuration
Block Diagram
Pin Configuration
INT7/P2.0
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDA1/SDI/SDO/P5.1
SCL1/SCK/INT2/P5.0
V
DD
JTDO
WSCF
V
PP
/WSCR
AVDD3
TEST0
MCFM
JTCK
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT0
P4.6/PWM6
P4.5/PWM5/SDA2
P4.4/PWM4/SCL2
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SUBYROMEM
I/O
PORT 0
SU
B
RET
S
I
G
ER
I²C
2)
PWM
D/A CON-
VERTER
SPI
I/O
PORT 4
I/O
PORT 5
Up to 96
Kbytes ROM
DATA
SLICER
& ACQUI-
SITION
UNIT
SYNC.
EXTRAC-
TION
Up to 8
Kbytes
TDSRAM
TRI
256 or 512
bytes RAM
STANDARD
TIMER
1)
TIMING AND
CLOCK CTRL
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
I/O
PORT 2
ADC
CVBS1
I/O
PORT 3
SYNC
CONTROL
VSYNC
HSYNC/CSYNC
ON
SCREEN
DISPLAY
FREQ.
MULTIP.
PXFM
NMI
INT[7:4]
INT2
256 bytes
Register File
ST9+ CORE
8/16-bit
CPU
Interrupt
Management
RCCU
OSCIN
OSCOUT
RESET
RESETO
P0[7:0]
WSCR
WSCF
CVBS2
R/G/B/FB
PWM[7:0]
SDO/SDI
SCK
INT0
STOUT0
MMU
MCFM
TXCF
TSLU
AIN[4:1]
EXTRG
P2[5:0]
P4[7:0]
P5[1:0]
P3[7:4]
CSO
HT
2
8
4
6
8
VOLTAGE
SYNTHESIS
VSO[2:1]
SDA1/SCL1
SDA2/SCL2
F_15160_048.eps
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